RGMII timing violation despite of false path

[SKon1]

Hello,

I'm constraining a double data rate RGMII input interface.

For reference - I'm using page 15 in this document:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf

In my case the PHY sending the data pre-shifts the clock (so I don't have to do it myself inside the FPGA).

These are my constraints:

# Create a 125MHz clock # virtual_source_p6: an ideal clock in the sourcing device # P6_outclk: input clock port of the interface; 90 deg phase shifted   create_clock -name virtual_source_p6 -period 8 create_clock -name P6_outclk -period 8 -waveform { 2 6 } [get_ports {P6_outclk}]   # Set input delay based on the requirements mentioned previously # P6_outclk is 90 deg phase shifted # Input delay is relative to the rising and falling edges of the clock   set_input_delay -max 0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outd*}] set_input_delay -min -0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outd*}] set_input_delay -max 0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outd*}] -clock_fall -add_delay set_input_delay -min -0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outd*}] -clock_fall -add_delay set_input_delay -max 0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outen}] set_input_delay -min -0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outen}] set_input_delay -max 0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outen}] -clock_fall -add_delay set_input_delay -min -0.8 -clock [get_clocks {virtual_source_p6}] [get_ports {P6_outen}] -clock_fall -add_delay   # Set false paths to remove irrelevant setup and hold analysis   set_false_path -fall_from [get_clocks {virtual_source_p6}] -rise_to [get_clocks {P6_outclk}] -setup set_false_path -rise_from [get_clocks {virtual_source_p6}] -fall_to [get_clocks {P6_outclk}] -setup set_false_path -fall_from [get_clocks {virtual_source_p6}] -fall_to [get_clocks {P6_outclk}] -hold set_false_path -rise_from [get_clocks {virtual_source_p6}] -rise_to [get_clocks {P6_outclk}] -hold

Although I set all the false paths as described in the document I keep getting timing violation between "virtual_source_p6" and "P6_outclk"

What am I doing wrong ?

[KhaiChein_Y_Intel]

Hi,

Can you share the design for investigation? What is the software edition (Pro/Standard) and version you are using?

Thanks

Best regards,

KhaiY

[SKon1]

Hi,

I'm using Q17.1 Standard.

I'll check if the design can be shared.

[KhaiChein_Y_Intel]

Hi,

Sure. Please keep me updated.

Thanks.

Best regards,

KhaiY

[SKon1]

Hi,

How can I share the design ?

[KhaiChein_Y_Intel]

Hi,

You may share a non-confidential design here by clicking on the attachment symbol and attach the design.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

May I know if you have any updates?

Thanks.

Best regards,

KhaiY