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17268 Discussions

ROM at ModelSim - data port is in High-Z State

Altera_Forum
Honored Contributor II
‎06-22-2013 12:50 AM
2,036 Views

Hi all. 

Im new to FPGAs. 

I have built some circuit with ROM memory (added with MegaWizard).  

The problem is memory output port is in the High-Z state all the time. I have connected clock to 50M clock, and address bus to 10-bit binary counter. 

I have "uploaded" ROM init state file also. 

Can you help me?
multiple-attachments.zip
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Altera_Forum
Honored Contributor II
‎06-22-2013 08:01 AM
1,169 Views

Do you have warnings in Modelsim related to unspecified ROM initialization file?

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Altera_Forum
Honored Contributor II
‎06-23-2013 07:42 AM
1,169 Views

I can't see nothing like that. But I attach all messages for query "ROM"

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Altera_Forum
Honored Contributor II
‎06-23-2013 08:53 PM
1,169 Views

Please help me, I will go crazy :| Timings are OK. Whats wrong with configuration?

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Altera_Forum
Honored Contributor II
‎06-24-2013 11:56 AM
1,169 Views

 

--- Quote Start ---  

Please help me, I will go crazy :| Timings are OK. Whats wrong with configuration? 

--- Quote End ---  

 

 

Configuration looks OK. Check Memory List in Modelsim.
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Altera_Forum
Honored Contributor II
‎06-24-2013 12:47 PM
1,169 Views

Memory list is empty. How I can load something? 

Also I noticed that warning: "Warning (113007): Byte addressed memory initialization file "127.hex" was read in the word-addressed format"
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