ROM lagging address by a full cycle?

Altera_Forum · ‎02-16-2015

I have a ROM implemented via megawizard and I noticed for some reason it seems to lag it's address by a full clock cycle, instead of loading the address present at the rising edge. The basic architecture is (using a switch as clock to allow for easy testing:


always @(posedge SW or negedge KEY) begin
if (~KEY) begin
addr <= 0;
else begin
addr <= addr + 1;
end
end
datamem data1(
.address(addr),
.clock(~SW),
.q(data_out));
assign LEDR = data_out;
assign LEDG = addr;

I have the ROM initialized with a .MIF file, and I can tell based on the lights, that even if the address on positive level of the switch is 0, it takes two cycles initially for the values to start coming out initially. The throughput becomes one per cycle, but the same thing happens if I reset at for example address 5, I can tell the address goes to 0, but the immediate following cycle I get address 5, and then I get 0. To test further I even switched the ROM to a different switch for the clock, and after any change in the address it takes a full cycle of the ROM clock to show the change. Any thoughts? Is this an option I can configure, or will the ROM by its nature have a full cycle of latency? I had been under the impression that as long as the clock frequency was slow enough, the ROM could output the data of whatever address is present, immediately following the rising edge, kind of like a flip flop. Is this understanding incorrect?

Thanks

Altera_Forum · ‎02-16-2015

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Is this understanding incorrect?

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Yes.

Read the megafunction user guide for the RAM component.

http://www.altera.com/literature/ug/ug_ram_rom.pdf

In addition to using hardware to learn about FPGAs, you should also learn to use the Modelsim simulator. It allows you to look at the design in more detail.

Download the zip file from post# 5 in this thread and run the Modelsim simulation

http://www.alteraforum.com/forum/showthread.php?t=35572

Its for a dual-port RAM, but you'll get the idea (its also written in VHDL, but don't let that scare you, just run the scripts and look at the Modelsim waveforms).

Cheers,

Dave

Altera_Forum · ‎02-16-2015

I've gone over the user guide before, but it never explicitly says if a READ requires a full cycle of latency, or if it can be read immediately. Am I wrong? I'm familiar with running modelsim, was just surprised at this behavior and was wondering if there's a solution that would let me read immediately. Is there?

Thanks!

Altera_Forum · ‎02-16-2015

--- Quote Start ---

I've gone over the user guide before, but it never explicitly says if a READ requires a full cycle of latency, or if it can be read immediately. Am I wrong? I'm familiar with running modelsim, was just surprised at this behavior and was wondering if there's a solution that would let me read immediately. Is there?

--- Quote End ---

What you are asking for is essentially asynchronous SRAM, i.e., the output data depends on the input address.

FPGAs contain synchronous SRAM, which is essentially asynchronous SRAM with input address, data, and control registers, and an optional output data register.

Use the IP Catalog (or MegaWizard generator on older tools) to create a single-port RAM component. Look at the little symbol it creates and you'll notice that the left-side (inputs) have registers, and depending on settings the outputs can also have registers.

This is a fundamental feature of the newer generation FPGAs, older generations like FLEX10K could have asynchronous SRAM, however, newer devices are "built for speed", and large asynchronous paths in SRAMs are slow, so those paths are cut with registers.

This "feature" is generally not a problem, since the address-to-read-data delay of 1 or 2 clocks is fine.

If that "feature" affects your design, then you could implement a RAM using logic elements. You'll want it to be small, but it will have the read timing you desire.

Cheers,

Dave