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Altera_Forum
Honored Contributor I
1,293 Views

RS232 UART not generated correctly in Quartus 17.0

I have a Quartus 16.1 project where I generated an "RS232 UART" from the IP Catalog and it worked fine. When I try to do this in a newer Quartus 17.0 project, it does not work correctly. I did a diff between the old and new generated core and the source of the problem is Quartus 17.0 is not using the correct clock to compute divisors.  

 

In both cases I generate it with Avalon Type = streaming, Baud = 115,200, parity none, Data = 8, Stop = 1: 

 

https://alteraforum.com/forum/attachment.php?attachmentid=13702&stc=1  

 

In Quartus 16.1 it generated fine, but now gives an error about the clock having to be specified at generate time: 

 

https://alteraforum.com/forum/attachment.php?attachmentid=13703&stc=1  

 

It is not at all clear where Quartus 16.1 grabbed the clock frequency from. The parameter editor does not have a value for it. However, it inserted a line in the UART.qsys file: 

 

<parameter name="clk_rate" value = "50000000" />  

 

that is not present in the 17.0 version: 

 

https://alteraforum.com/forum/attachment.php?attachmentid=13704&stc=1  

 

This caused the file UART\synthesis\submodules\uart_rs232_0.v to have 0 values for certain counters: 

 

https://alteraforum.com/forum/attachment.php?attachmentid=13705&stc=1  

 

When I manually edit these to be correct, the UART functions again. But something happened in 17.0 to make this not generate correctly. Again, it's not at all clear where the core gets the clock frequency from in the first place (in 16.1 or 17.0).  

 

I always seem to have trouble uploading images. They always appear tiny.
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6 Replies
Altera_Forum
Honored Contributor I
85 Views

Based on your description and the tests you've tried, this sounds like a bug. Raise a ticket via myaltera (https://www.altera.com/mal-all/mal-signin.html). 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
85 Views

Yes, I've done that but don't have high hopes :-). I've found knowledgeable users tend to be my best bet. I have a workaround so it's just one of those annoyances that sucked up a couple hours of my time for no reason (assuming whatever caused this issue does not break other things in 17.0).

Altera_Forum
Honored Contributor I
85 Views

Do you need Q17.0? I'd revert back to Q16.1 until a service pack exists for Q17.0, or Q17.1 is released. That'll iron out all the bugs they've introduced into Q17.0. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
85 Views

a_x_h_75, 

 

So far, this is the only issue I've had with Q17.0. Altera upgrades are usually pretty easy at least for me (very different from my experience with Xilinx where I dreaded them).
Altera_Forum
Honored Contributor I
85 Views

Alex,  

 

I'm using 17.2 and there is the same problem. I have a design that was done in 16.1 and I'm facing the same problem as a_x_h_75. It is not just the upgrade, but even if I delete the IP and create a fresh one with 17.2. 

 

a_x_h_75, You said that yo modified the UART.qsys file and were able to successfully compile? Well, I'm not able to do that even after adding the clk_rate entry. Could you please let me know the steps for successful compilation?
Altera_Forum
Honored Contributor I
85 Views

It sounds like the bug is still there. Raise a support request (having confirmed the issue is still present in the simplest of simple designs). 

 

Cheers, 

Alex
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