Hi All,I want to use the different library names for the same Le's say I have a VHDL file with the following lines: library mylib_1;use mylib_1.abc.all; But, when I'm going to use the same file for another design, I want this library will be named differently: library mylib_2;use mylib_2.abc.all; I don't want to edit this file depending on what design this file is going to be used. So, how should I manage this issue? Is it possible to do this using configurations? How? Thank you!
Why would you want to change the library name? libraries should be collections of related items. Eg. my_math_library would probably contain items that do maths functions. My_axi_lib would contain axi related items. It wouldnt really make sense to have different library names in different projects.Configurations wouldnt really work, as they still expect a known library name. In modelsim you can use the vmap function to map a library to another library, but that wouldnt help if you were refering to mylib_1 inside mylib_2. So try and explain why you're trying to do what you're doing?
"try and explain why you're trying to do what you're doing?" - for different projects, the unit should be compiled into different libraries (library nabes)."In modelsim you can use the vmap function to map a library to another library" - probably this would be a solution, but as you stated below "but that wouldnt help if you were refering to mylib_1 inside mylib_2" - is it possible to refer to a package in the library without stating the library name (just a path to the package, like a relative to the directory) For example, use ../../mypkg.all
In Verilog, there is "`define" where the names/paths might be definedIn VHDL, there are generics. But as far as I understand, they canoot help in this case... The import package (like in SystemVerilog) is there something similar in VHDL? In VHDL, can I include different files (like `include in Verilog) depending on configuration?
import package my_pkg in SV is equivalent to use my_pkg in vhdl.Compiling a unit into multiple libraries is perfectly fine. Whats the problem here? vcom -work my_lib1 abc.vhd vcom -work my_lib2 abc.vhd Now abc exists in both libraries. remember, you can refer to items in the same library using work. Work is not a library itself, it can be thought of as a "local library" So, why not post some code with what you're trying to do. Compiling the same thing into multiple libraries seems like an odd concept to me. A library should be a static thing containing static objects. I dont understand why you would want it in another library.
VHDL has no pre-compiler, like# directives in C or ` directives in verilog. in a `include abc.vh, All these do is literally copy the text from abc.vh into top_level.v and then compile the file.