RTL Viewer

[Altera_Forum]

Hi. 

If I have one file written in VHDL with two different architectures could I see in RTL Viewer structure for each architecture? or the architecture shown in rtlviewer wil be randomly selected by quartus?

[Altera_Forum]

Mind elaborate on "two different architectures" here?

[Altera_Forum]

If I make two separte files I can achieve the desired. but I want to have only one file. 

@nic_@ yes, here you can understand about you adders and comparators, and register structure too. The early you undesrstand what you can get the early you achive the desired structure. If you experienced user in FPGA you tend to write program as template. Yoo should do like "this" to achive "this". Analysis and Elaboration - iterative process until you get someone that meet you. After that you can do fitting, optimisation, synthesis. So to reduce number of Analysis and Elaboration steps just make as many architecture as you can than look at the result and choose what is suitable for you.

[Altera_Forum]

architecture is selected when you instantiate the entity. If you do it via a component you need to use a configuration to select the appropriate architecture  

  component my_comp is .... for all: my_comp use entity work.my_ent(arch_sel);   Or better, use direct instantiation:  inst1 : entity work.my_ent(arch_sel);   If you have two architectures at the top level, apart from asking why, I dont actually know how Quartus behaves. Multiple architures, when used, are only usually used for differentiating a simulation model of an entity verses a RTL implementation. I have never used multiple architectures and it is highly discouraged in industry. If you want different behaviours then create different entities (or use generics to control behaviour).

[Altera_Forum]

I do not what different entities at design.  

@Tricky, you are right - use configurtion but do it as late as possible. How you can control structure through "generic" you will should used "generate" after all? it is better to write procedure/fucntion. but it is another level of programming. Okay. How many architecture you could provide for full-adder for 3 32-bit words or for 6 64-bit words? How you can compare it in one step in design cycle/what about simulation. WE stop here and say for ownself "there a lot of ready-made code. why not just using it". I answer for myself "let's modify that code to meet my project requirments".

[Altera_Forum]

--- Quote Start ---  I do not what different entities at design.  @Tricky, you are right - use configurtion but do it as late as possible. How you can control structure through "generic" you will should used "generate" after all? it is better to write procedure/fucntion. but it is another level of programming. Okay. How many architecture you could provide for full-adder for 3 32-bit words or for 6 64-bit words? How you can compare it in one step in design cycle/what about simulation. WE stop here and say for ownself "there a lot of ready-made code. why not just using it". I answer for myself "let's modify that code to meet my project requirments".  --- Quote End ---    Just instantiate two adders instead of two architectures and assign to two outputs. In practice I never need to do more than one architecture. Universities love it.

[Altera_Forum]

So. What does style depend on? 

@kaz, your advice good, add it to @Tricky and we get "make as many architecture you want, then make new entity where all desired architecture instained through configuration or direct instance. Enjoy". I 'll get one file with all desired architecture that wlll be a parallel structure .  Open any Viewer (RTL,Topology) and "enjoy" (sarcasm). Is it convenienced for me? It 's better to add in quartus ability to choose which architecture(s) to open. I don't like the way that exist for today.

[Altera_Forum]

It only compiles a single architecture. There is no point compiling multiple architectures as only 1 is ever used at any one time. If you want to view each one you will need to compile the design twice.

[Altera_Forum]

@Tricky, you understand . only one architecture but which one, it seems it uses one that latter in the file. 

to get the second you should use another entity where you instained two componets. Is it convenienced? Research/design cycle becomes longer at this stage - to get rightfully adjusted vhdl code. As alternative - we all together pointed it out in the thread. We should think of "when your experienced you don't bother with such question 'how to' cause you know time-prooven designs"

[Altera_Forum]

Look up how to write configurations. You can put them in a separate file to control which entities use which architecture. 

 I suggest you stop using separate architectures. Your other posts also suggest you are trying to write code against convention.  If you want to raise issue with the way the tools work, you need to be raising the issue direct with altera.

[Altera_Forum]

--- Quote Start ---  Look up how to write configurations. You can put them in a separate file to control which entities use which architecture.  I suggest you stop using separate architectures. Your other posts also suggest you are trying to write code against convention.  If you want to raise issue with the way the tools work, you need to be raising the issue direct with altera.  --- Quote End ---    1 line. it is acceptable 2 line. I can stop use separate architecture , but if I find any mistake in design i should go step-by-step to remove one.  convention could help reduce mistakes. but fully-qualified condition in if-statement and nested-if that cover the same input set produce different results. even more you can get a lot of multiplexors instead of good scheme. thats belong to "how to write code right". 3 line. raising ticket. "Improve your software. Give me more VHDL support". I understand why only one architecture . look at verilog , schematic... but it is not true for vhdl. I think for now software cut off power of VHDL.

[Altera_Forum]

If your code produces different results on every compile, then I suggest there is a problem with your code and practices. I never get "a lot of muxes" - I get exactly the hardware I expect. 

 You can only implement 1 architecture because it has to go into an FPGA. an output can only connect to one set of logic. You need extra logic to connect multiple architectures to an output, which would need to be defined in the VHDL, so you need somewhere that specifically selects the individual architectures.  The VHDL has to map to the hardware available. Not all VHDL is going to map to the hardware. No ammount of tickets is going to make that happen. So far, I fell like you're trying to write software rather than hardware.

[Altera_Forum]

by the way, RTLView helps to find mistakes in code and provides some information about which path for data could be time-critical. 

so you can change design before you will begin fitting.

[Altera_Forum]

@Tricky, I try to stay at top-level of abstraction. if I have trouble on the very first stage , why proceed to the second? I want the first stage will be comfortable. 

When you end up debugging your code and quality of syhthesis is quite good for you then you have only 1 architecture which will be programmed in FPGA. but how you will select the one architecture and say "it is good". do you know about it from the very start of project? if so you have experience (green, yellow, red marks under your name at forum ;) )

[Altera_Forum]

It's quite easy to work out the timing critical paths from the code. The largest amount of logic between registers will be the culprit.  

I hardly ever use the rtl view unless I think there is some synthesis bug.

[Altera_Forum]

The best way to find mistakes in code is via simulation. That is the most efficient debug tool.

[Altera_Forum]

okay. the usage depends on background knowledge. You certain about your code - you don't use tool, but not me. 

What i want i've already said (maybe sad ;) ). Tool usage depends on one's own.  the question still exist: if quartus compile as expected as many architecture as written why it can not open choosen one until you choose it explicit?  P.S. : I couldn't change my knowledge at speed of modern FPGA.

[Altera_Forum]

--- Quote Start ---  @Tricky, do you know about it from the very start of project? if so you have experience (green, yellow, red marks under your name at forum ;) )  --- Quote End ---    You haven't seen FvM's rank, he is the highest decorated Altera lieutenant.  I think the best tool is you and that requires familiarity with tool and concepts. I wouldn't go your way to know ahead of fitter. I will design with minimum logic in between registers and pray. One design with its files and dependencies is far too much. If you are dealing with large projects contaings 100s of design module I wonder how can you design several versions just for testing. Where is Practicality, time factor, manager's mode???

[Altera_Forum]

@kaz, @tricky 

we can end up with "why such tool exist?" and "why vhdl allow multiple architectures?")) multiple architectures exist but it seems noone want to deal with it. it is subject to thread in VHDL section/not here. When you have time to research or ,for example, you have good partner. why not? Even in "advanced synthesis book" there are several approach to adders/compressors, you choose only one for one entity or choose as many as you want, then make a final decision. Will you put in one file or among many files? will it be library at all?  i got answer how i can manage with my question in current environment. it is good enough. and it seems that thread for now is mixed up with "usage rtlviewer tool" and "using vhdl architecture concept". Due to the very first question. I appologize that you can not over-persuade me to take your position at 100%, but 70% :)

[Altera_Forum]

--- Quote Start ---  @kaz, @tricky we can end up with "why such tool exist?" and "why vhdl allow multiple architectures?")) multiple architectures exist but it seems noone want to deal with it. it is subject to thread in VHDL section/not here. When you have time to research or ,for example, you have good partner. why not? Even in "advanced synthesis book" there are several approach to adders/compressors, you choose only one for one entity or choose as many as you want, then make a final decision. Will you put in one file or among many files? will it be library at all?  i got answer how i can manage with my question in current environment. it is good enough. and it seems that thread for now is mixed up with "usage rtlviewer tool" and "using vhdl architecture concept". Due to the very first question. I appologize that you can not over-persuade me to take your position at 100%, but 70% :)  --- Quote End ---    Well I came to the conclusion that yes learners need different version of tools in order to learn best way. So yes I agree that having support for multiple architectures in one compilation will help. Altera wants profit and is not a charity. Universities need to raise issues like that and other issues like many beginners use buffer type io or bit type instead of std_logic. May be just the old things went through University programs, each professor copying his colleagues's previous slides. I am persuaded 100%

[Altera_Forum]

The statement of "multiple architectures exist but it seems noone want to deal with it" is incorrect, in fact configurations are covered in the first section of the LRM! 

 Similarly if you have create multiple architectures and they are always all compiled will mean that every architecture must be syntactically correct or the compilation will fail. I think this would cause more (justifiable) criticism than the way it currently works.  At the end of the day the vendors tools are limited by the LRM and the functionality of their competitors' tools, irrespective of who they are.