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Hi,
Quartus Version : 22.2.0.94
A "Multi Channel DMA Intel® FPGA IP for PCI Express" IP is integrated with AXI4 DUT and On Chip Memory.
Data Responses for BAR2 MMIO read requests are not reaching PIO interface.
The attached "NoReadResponseAtPIO.png" shows
=> a valid Read response is present on DUT AXI interface.
=> rx_pio_waitrequest_i goes low
=> rx_pio_readdatavalid_i does not toggle.
This results in a hang in mm_interconnect. Subsequent read/writes initiated on rx_pio does not pass through mm_interconnect.
How can we overcome this issue?
Regards
Siva Kona
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Hi,
The PIO is always mapped to BAR2, see 3.1.4. Avalon-MM PIO Master:
See also 4.1.1 which mentions the addressing:
BAR0 is always used for the Control Register Block (CSR), see 3.1.9. Control Registers
The Bursting Avalon-MM Master (BAM) can be mapped to any BAR other than 0, see 3.2. Bursting Avalon-MM Master (BAM)
8.2.7 API List, table 97 to 100 detail the PIO API format:
Our Example Design can be generate to include a PIO Master on BAR2, as a starting point you may want to generate and refer to that:
Regards,
Wincent_Intel
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Hi Wincent_Intel, Good Morning!
We have generated an SOF with Quartus Version 22.3 and observed the same behavior to persist.
The issue is NOT resolved yet. Request you for further inputs.
Is this behavior due to issues in mm_interconnect or PCIe Endpoint?
Regards
Siva Kona
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Will close here as the communication move to private.
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