Reading Data in PC from MAX10 FPGA board

[Altera_Forum]

Hello everyone, 

 Greetings. I'm pretty new in FPGA area and I need a few direction in the right path to proceed with my ongoing project. I'm using MAX 10 evaluation kit and Quartus ii 15.0 web edition as software.  I'm trying to read data (more specifically bit error rate ) in MATLAB from my FPGA board. I've already installed DSP builder. However I'm concerned with how I should create the interface between PC and FPGA board using the IPs. I have to communicate through the JTAG. I've thought about two methods but really confused which one to adapt.  (i) I have created my design as avalon mm slave using the slave template provided in altera's website in Qsys. I just added the code for using slave template code with my already existing code. Than I connected the MM slave with JTAG to Avalon MM bridge. However, I think I will run into issues by doing that. First, by creating a slave , I can write or read an address. In my project , all I'm trying to do is read from a memory in the FPGA to PC. So, if I use slave memory address to read, it has to be written first. Can I do the writing in Avalon MM Slave by implementing a custom write function? I can write into an address by using M.write() function in Matlab but that's not what I'm looking from. I have to write the BER in an address and than read calling M.read() function. And writing the BER has to be done from FPGA. But is it possible to write into an avalon mm slave address from the FPGA.  (ii) AVALON ST Source: Since my data transfer is unidirectional (fpga to PC ) I am thinking about using an AVALON ST source. But I'm having a hard time figuring how to do that. Can I use AVALON ST source streaming and connect with JTAG to AVALON MM master bridge? Then will I be able to read the data in PC?  Thanks for patiently reading this long post. I will appreciate any comment that will put me in the right path.  -Taufiq

[Altera_Forum]

Communication between PC and FPGA can be done via UART - just use the rs232 uart module in qsys. You will need to connect it to an avalon master like nios. Then you can write data to the uart module which will spit it out at your desired baud rate on 2 pins (UART RX and TX). You can buy a simple UART to USB converter for under $5 to interface to the USB port on the PC. 

 What exactly are you doing with DSP builder? If you have some values you want to connect to avalon memory map from DSP builder you can use RegFields (look it up the the DSPBA manual). This will let you write values to specified address location in the memory map. You can then use NIOS to read those values and write them to UART.

[Altera_Forum]

--- Quote Start ---  Communication between PC and FPGA can be done via UART - just use the rs232 uart module in qsys. You will need to connect it to an avalon master like nios. Then you can write data to the uart module which will spit it out at your desired baud rate on 2 pins (UART RX and TX). You can buy a simple UART to USB converter for under $5 to interface to the USB port on the PC.  What exactly are you doing with DSP builder? If you have some values you want to connect to avalon memory map from DSP builder you can use RegFields (look it up the the DSPBA manual). This will let you write values to specified address location in the memory map. You can then use NIOS to read those values and write them to UART.  --- Quote End ---     Thanks a lot krasner. I was actually trying to do it with on board usb blaster ii. But I guess I should try rs232.   DSP builder comes with MATLAB API. I was just looking a way to communicate via MATLAB.

[Altera_Forum]

I should elaborate my idea about how I will do it. 

 I have already a system built in schematic editor that generates some data. I'll write the data after certain time in a memory and I need this data to get on my PC. So how I'm going to integrate my custom design with rs232 ip core in Qsys? Should I generate a hdl code from my custom design and add the code for rs232 ip core at the end? Then I synthesize the rewritten hdl in Qsys? I am failing to grasp the idea how an avalon master such as nios2 should be used in my qsys design?  Thanks in advance.

[Altera_Forum]

a quick ready made solution is using in system memory editor. you read/write to pc through this editor (which uses the jtag feature and a gui). You will need to instantiate the ram with this option in order to use the feature.

[Altera_Forum]

--- Quote Start ---  a quick ready made solution is using in system memory editor. you read/write to pc through this editor (which uses the jtag feature and a gui). You will need to instantiate the ram with this option in order to use the feature.  --- Quote End ---    Thanks a lot.

[Altera_Forum]

--- Quote Start ---  Thanks a lot krasner. I was actually trying to do it with on board usb blaster ii. But I guess I should try rs232.   DSP builder comes with MATLAB API. I was just looking a way to communicate via MATLAB.  --- Quote End ---    When you use Bus (ModelBus Library) related blocks in your DSP builder design, when you generate the VHDL code and generate the qsys module, that module will have an avalon slave port associated with that bus. Avalon slaves are connected to avalon masters. In this case, your avalon master can be the NIOS II data master. NIOS II's data master will also connect to the UART RS232 module's avalon slave port. This way NIOS can read data from the DSP module and write it to the UART module.  Alternatively, you can use hardware in a loop to run fpga and matlab together via System Console and Matlab API (https://www.altera.com/en_us/pdfs/literature/wp/wp-01208-hardware-in-the-loop.pdf). I've never done this, so I can't say if this will be helpful to you.  I've used the former process (via NIOS and UART) successfully.