for my design I'm using the Intel Transceiver PHY IP Core which I connected to an Ethernet PHY. The 625 MHz input tx_serial_clk for the Transceiver PHY is generated by the Transceiver ATX PLL, which I connected via the ALTCTRL IP to the serial clock input of the Transceiver PHY IP.
So my problem is, when I compile my design I get the following Error message:
ERROR (16765): Clock buffer "Clk625ctrl_i|altclkctrl_0|Clk100ctrl_altclkctrl_181_w5grwea_sub_component|sd1" is incompatible with the required global signal types of its destination ports. Modify your design to change the clock buffer type for the specified signal or the required global signal type of the destination nodes.
I could not find a solution to fix this error and I hope someone can help me with this issue.
I'm using the Intel Quartus 18.1 Pro Edition and developing for the Intel Cyclone 10 GX FPGA.