Recompilation after modifications in signaltap

[Altera_Forum]

Hello everybody, 

 I'm facing a long compilation times issue in Quartus everytime I make any modifications in the signal set (i have a Nios II + custom coprocessor system which takes more than 1 hour to compile).  Do you know if there's a way to avoid recompiling the whole system? If I try design partitions I somehow get lots of error about what i think are some signal encapsulation requirements.  Thanks a lot

[Altera_Forum]

Hi, when you use SignalTap, you have a switch named "Allow all changes / allow triggers changes only" (something similar) above the data settings in order to not recompile the whole 

BUT you can't change the signal set anymore except triggers, transitional save...  Put a wide set of signal, after you will opt what you want.  In Quartus 12.0sp1, I face to a little problem : SignalTap sometimes does not recognize my trigger conditions, I have to save and reload.

[Altera_Forum]

Well, I don't have much free BRAM on my device so I can't have such a wide set of signals. I don't think I can ignore some signal logging afterwards either, is that right?

[Altera_Forum]

Since SignalTap has to re-routing the FPGA, It is hard to compile partitions only. 

Since Signaltap needs a compile, so as the FPGA to be configured, ignoring signals afterwards will not optimize the FPGA ressources.  For a work around, as i said, you can set a wide range of significant signals, You can change your signaltap clock to a slower "clock" You can use transitional storage ...