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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Sample Depth for Signal Tap

Altera_Forum
Honored Contributor II
‎04-01-2014 09:15 AM
2,118 Views

Quartus II puts an upper limit on the sample depth to 128K samples to be captured using the signal tap. I wonder whether there is a way to increase it when internal FPGA RAM is available for this purpose e.g. increasing the depth to say 1024 K samples.  

 

Regards, 

 

Alpha
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Altera_Forum
Honored Contributor II
‎04-02-2014 06:01 AM
1,386 Views

Why don't you try it out and let us know the result! If you edit the stp file directly in a text editor, you can find this string: sample_depth="128". Change 128 to 1048576. You'd better compile with the changed stp file before opening it up in editor. Possibly, you have to even use the tcl shell to acquire before opening it up in editor. Just guessing.

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