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Regarding PLL issue.....

Altera_Forum
Honored Contributor II
‎03-11-2010 12:45 PM
1,037 Views

Hello Frinds, 

 

I m using Cyclon Device for my Project with quartus II-9.1.  

now in my system i need one pll for altera sdram controller to provide clock with phase shift of -3.51 ns (as par datasheet of sdram -3.35 ns). 

 

if i m using above PLL setting inside SOPC then my whol system working as par needed without any error. 

 

But if i m using this same PLL in BDF level (outside SOPC Builder) then SDRAM hang during operation. 

 

When i m changing PLL phase shift at BDF level (replace -3.35 ns with -3.90 to above) then system working as par needed without erros. 

 

So can anyone tell me y same PLL phase shift not working in BDF level (means in SOPC phase shift -3.35 ns and need to change in BDF level for proper working)??? 

 

what is possible reason behind this type of problem?? 

 

Regards: 

DG
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