create user IP with inside-fixed placement (like LogicLock)?

[Altera_Forum]

Hi, for a time-to-digit block i.e. Vernier delay line for pulse timing interpolation measurements, is there some way in Quartus Web Edition for creating custom user IP with a fixed inner relative placement of the RTL / low level primitives? 

 For example "Vernier IP" for some specific Cyclone/StratixFPGA series consisting of a block of say 16 LCELL all immediately next to each other, with DFF register below, none of primitives optimized away, but still more or less freely placeable (as a block) anywhere on the FPGA?  Is there some method to create such semi-fixed IP in Quartus or tools?  In theory what I look for is a bit like the LogicLock, except for Web Edition if possible, without X11_Y22 etc hard placement constraints, and with multiple instantiation so I can slap a few of these IP "blocks" randomly around the FPGA. Is it doable, or asking for the impossible? :)

[Altera_Forum]

I think it is possible but with the X11_Y22. 

 It is easily doable inside generate statements in both VHDL and Verilog

[Altera_Forum]

Thanks for pointers.  

 I tried to read up a bit more and Quartus doesn't seem to support Xilinx-style RLOC relative location constraints which'd make this very easy.  Though as you point out, via generate, and then maybe corner for absolute location start given as module parameters it seems well not entirely luxurious but at least more or less easily doable!