--- Quote Start --- See http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html --- Quote End --- This tcl may be a quicker way of getting timestamp and writing it as constant into a package. # open time stamp VHDL file
set fp
# get current date & time (yymmddhhmm)
set str_ascii -format {%y%m%d%H%M}]
# write to above VHDL file
puts $fp "library IEEE;"
puts $fp "use IEEE.std_logic_1164.all;"
puts $fp "use IEEE.numeric_std.all;"
puts $fp \n
puts $fp "package Timestamp is"
puts $fp " constant TIMESTAMP : std_logic_vector(31 downto 0) := std_logic_vector(TO_UNSIGNED($str_ascii, 32));"
puts $fp "end package;"
close $fp
Just share with people with TCL file for verilog version # # # you must add the following line into your QSF file# # set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:./create_timestamp.tcl"# # # # open time stamp Verilog file
set fp
# get current date & time (yymmddhhmm)
set str_ascii -format {%y%m%d%H%M}]
set show_ascii -format {%Y %b %d %I:%M:%S %p}]
# write to above VHDL file
puts $fp "\/\/\tyou must add the following line into your QSF file"
puts $fp "\/\/"
puts $fp "\/\/\t\t set_global_assignment -name PRE_FLOW_SCRIPT_FILE \"quartus_sh\:\.\/create_timestamp.tcl\""
puts $fp "\/\/"
puts $fp "\/\/\tCompiling Date: $show_ascii"
puts $fp "module timestamp(dout);"
puts $fp "\toutput wire \ dout = 32\'d$str_ascii;"
puts $fp "endmodule"
close $fp
