I want to include a text file I want to read and write to. However, verilog is unable to find the text in the current directory. How do I determine relative path in System Verilog.
I have tried the following with no luck(for reading only) and none works.
file = $fopen("data.txt", "r"); file = $fopen("./data.txt", "r");
However, absolute path works though, but that is not what I want.
My bad. So basically I am using a tool(connects to modelsim) which automates the simulation of this design module against a testbench. So it works with the individual files as opposed to the project file. This could be the problem.