Reset Read/Write address of ALTSYNCRAM using aclr (FIFO)

[Altera_Forum]

Hello, 

 Can someone please tell me how I can reset the read & write address of an ALTSYNCRAM, Altera Megafunction??  I am simulating using ModelSim where I control the "aclr" using a register "reset_reg". I want the read/write address to be reset to '0' when the "reset_reg" goes high. Unfortunately, this doesn't seem to work at the moment and I don't know why.  Any help would be very great!

[Altera_Forum]

Remember address is input to ram and it is up to your logic to reset it. 

aclr, as I believe is the data reset of your ram.

[Altera_Forum]

Hi Kaz, 

 Yes, I understand your point.   Initially, I tried to manually reset these addresses. But, I was not able to reset both "read address" & "write address" at the same time (clock). Only one of them reset. Again, I was not sure why?  So, I saw an option in the Altera megafunction setup where I can mention which ports (read address, write address, read enable, etc) should be reset when "aclr" is triggered. This also has not worked.

[Altera_Forum]

post your reset code (process)

[Altera_Forum]

Aha, I see your point. aclr can clear any register inside ram function. However you would not see that at input i.e. address going into ram. You better apply your own reset to the addresses since they are inputs to Ram

[Altera_Forum]

Thanks for the support Kaz, it worked now when I manually reset the addresses. 

 Cheers!