Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Retiming inside LPM_DIV

Altera_Forum
名誉コントリビューター II
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Hello all, 

 

From my test Quartus can't move registers inside math of LPM_DIVIDE inferred automatically. 

There is a way to do it? 

 

Thank you
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Altera_Forum
名誉コントリビューター II
703件の閲覧回数

The LPM_DIVIDE IP does cater for pipelining. However, how you infer that I don't know. I suspect you'll have to use the MegaWizard. 

 

You won't be able to insert registers 'part way' through the calculation unless you infer two LPM_DIVIDE blocks to perform the calculation required and I doubt that'll gain you anything. 

 

Cheers, 

Alex
Altera_Forum
名誉コントリビューター II
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Nope - you have to instantiate a MW core rather than inference. 

This issue has been around a long time - I raised an enhancement request for this about 6 years ago. Still waiting...
Altera_Forum
名誉コントリビューター II
703件の閲覧回数

Using synthetizers like synplify retiming works. 

it seem a limitation of quartus that can't do retiming inside IP block.
Altera_Forum
名誉コントリビューター II
703件の閲覧回数

 

--- Quote Start ---  

Using synthetizers like synplify retiming works. 

it seem a limitation of quartus that can't do retiming inside IP block. 

--- Quote End ---  

 

 

Please raise an enhancement request with altera.
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