Reversing bits in a bus in verilog...

[Altera_Forum]

I was wondering about the easy way to reverse bits in a bus in Verilog. Here is the code I wrote: 

 ------------------------------------------ if (rev) begin  out[29:0] <= inp[0:29]; // Reverse video data buss bit order  end else begin // !rev  out[29:0] <= inp[29:0]; // Normal video data buss bit order  end -----------------------------------------  The second line came up with a compile error: Part select direction is opposite...  Is there a quick way to do this without writing out each wire?

[Altera_Forum]

In VHDL a for loop is necessary for the bit reversal, I think, it's also the case in Verilog.

[Altera_Forum]

--- Quote Start ---  In VHDL a for loop is necessary for the bit reversal, I think, it's also the case in Verilog.  --- Quote End ---    Are you saying to place : --------------------- for ( n=0 ; n < 30 ; n=n+1 ) begin  out[n] <= inp[29-n]; // Reverse video data buss bit order  end -------------------- in place of the -> out[29:0] <= inp[0:29];  I'm assuming my Verilog use of a 'for loop' here is correct....

[Altera_Forum]

Yes, it looks OK.

[Altera_Forum]

welll.. there's a bug in Quartus ... 

if you have: wire [9:0] a; wire [0:-9] b;  then: assign a=b; causes a flip.

[Altera_Forum]

If you can use SystemVerilog, its simple to use the streaming operator 

 out = {<<{inp}}; // right to left streaming

[Altera_Forum]

--- Quote Start ---  If you can use SystemVerilog, its simple to use the streaming operator  out = {<<{inp}}; // right to left streaming  --- Quote End ---    Since this post is under "Quartus II," it's worth noting that Quartus does not support the streaming operator. It is still listed as "unsupported" in Q12.0:  http://quartushelp.altera.com/current/mergedprojects/hdl/vlog/vlog_list_sys_vlog.htm  (See section 11)  I tried it just for kicks and got a syntax error. ModelSim recognized it, though.