Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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I would like to know how can i prevent the quartus II analysis and synthesis tool to generate interface I/O buffers that connect input /output pin to logic design. Thank you
To remove I/O buffers you need to assign the input and output ports as Virtual pins expect clock,reset and Transceivers. It will do the trick but it will be ignored if your interface is a bidirectional one.
