Ring Oscillator Help!!!

Altera_Forum · ‎05-09-2007

Hello.I am from Greece.And i have find this forum today.I must design a project at university, But i have a problem.The project is to make Capacitance to Digital Conversion, so i must design a logic circuit and measure variable capacitors.I was thinking to create a ring oscillator and to connect a variable capacitor between ring oscillator and ground.More capacitance ,lower frequency.The problem??? The Ring Oscillator frequency without capacitor is at least 125Mhz very HIGH!!! I believe that the solution (slow down frequency) is to add more stages (for example 101,1001) but Quartus 7 web edition optimize my design and cancel all of the inverters.The frequency of a ring oscillator general is:

Fmax=1/n*Td

n:stages R.O.

Td=Time Delay

of each inverter

I use UP2 programmer in MAX fpga.

HOW can i disable optimization???????????

Thank you!!!!

Altera_Forum · ‎05-10-2007

You must cascade each inverter with an LCELL primitive insertion. Then you must set the Remove Redundant Logic Cells option to OFF for the top level design.

BTW - another design for self oscillator is the RC + schmitt trigger input on MAX II. The MAX II dev kit has pads for an RC network to connect to the MAX II input for oscillator behavior. The freq depends on the RC value and threshold points fo for the MAX II schmitt trigger input. I can't remember what those were or what you get, but you can experiment with it. The equation is written in some schmitter trigger RC write-ups.

http://www.fairchildsemi.com/an/an/an-140.pdf

Also check the MAX II dev kit datasheet for schmitt trigger RC.

Altera_Forum · ‎05-10-2007

Thank you Joe D i will try to work with your settings...