After synthesis, Fitter terminates due to routing congestion .
Average interconnect usage (total/H/V) 40.3% / 38.1% / 47.0%
Peak interconnect usage (total/H/V) 69.8% / 67.2% / 78.1%
Maximum fan-out 93034
Highest non-global fan-out 3773
Total fan-out 765512
Average fan-out 3.69
Warning (16684): The router is trying to resolve an exceedingly large amount of congestion. At the moment, it predicts long routing run time and/or significant setup or hold timing failures. Congestion details can be found in the Chip Planner. Warning (16618): Fitter routing phase terminated due to routing congestion. Congestion details can be found in Chip Planner. Error (170143): Final fitting attempt was unsuccessful
Please answer my below queries:
1) How to address this issue ? I referred to optimization document, but only understood and I could just address threshold level and view the chip layout in chip planner ? I didnt understand how to see what signals , in which module has high fan-out /routing etc? please help me with this. Document which i refferred is below:
Intel® Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization
2) Is there some detailed report showing routing signals?
3) Can I find out which module is causing high routing congestion?So that I can change the coding style of that particular module .
You may report the routing utilization in the chip planner.
The routing congested area will be shaded in pink/purple. You may check which module is placed at that location.
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