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Valued Contributor III
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SDC constraint warning messages during synthesis

Hi, 

 

I got three things on my mind right now:  

 

1) after finally getting a hang on how to constrain a design using TimeQuest, I run into huge amounts of warnings that are put out during synthesis, for example:  

 

Warning: Ignored assignment: set_input_delay -add_delay -max -clock [get_clocks {inst1|altpll_component|pll|clk[2]}] 3.700 [get_ports {I2C_SDA}] 

Warning: Argument <targets> is an empty collection 

 

The same constraint works fine using TimeQuest or when the fitter is running. Now, do I get those warnings, because there is not netlist yet, from which the synthesizer can get said ports? Also, I have timing driven synthesis deactivated, still I get the error messages. I choose to ignore then, since my design seems to work as intended and TimeQuest does not find any problems later on. 

 

2) On another note, I am really annoyed by the altera_reserved_tck constraint that is hidden in some megafunction I use (probably probe or signaltap) and that I cannot edit: 

 

Warning: Ignored assignment: create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}] 

Warning: Argument <targets> is an empty collection 

 

I use this constraint I got from the support database and overwrite the hidden one and that does not produce a warning message: 

 

create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck} -add 

 

Still, is there no way to get rid of hidden constraints? 

 

3) I sometimes get weird setup relationships on my clocks of 0ns (basically latch and launch edges are identical).This only applies to the path from a dff to an output pin. I use this constraint to generate the clock: 

 

create_clock -name {TXCLK} -period 80.000 -waveform { 0.000 40.000 } [get_ports {TXCLK}] 

 

which is nothing special really. The output is constrained in the skew approach (according to Altera online training) as follows: 

 

set_output_delay -clock { TXCLK } -max 38 [get_ports {TXDATA* TXEN}] -add_delay 

set_output_delay -clock { TXCLK } -min -38 [get_ports {TXDATA* TXEN}] -add_delay 

 

Basically, an UDP/IP-streaming core I use outputs it's tx data to one row of dffs which output the data to the output pins. The hold violation of 0ns I get is from dff to output pin. This violation only happens with 12,5MHz TXCLK which is used in 10/100Mbps mode and is an external clock from the PHY. In 1000Mbps mode, the pll generated 125MHz clock is used and no violation occurs. 

 

OK, that's all for you gurus ;) My design works fine, but I am trying to shave off the rough edges and cut down on the less important warnings during full compilation.
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