SDC file for clk from Native Phy

[iiwan]

I have design(modules), that works on rx_clkout, tx_clkout pins from Transceiver Native Phy (Stratix V). And dynamically reconfigure Native Phy to speeds 5 gbps, 10 gbps from 2,5 Gbps. So my disign compiles according clk from 2,5 gbps. How make SDC file, to tell quartus, that my modules have to work good on 2,5 , 5, and 10 gbps. According to speed and bus wide freq is 62,5 , 125, 250 Mhz.

P.S. my previous post about it https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-tell-quartus-for-multiple-clock/m-p/1187216/highlight/true#M17849

[Kenny_Tan · Accepted solution]

Sorry that it was a bit late on the reply,

In Timing anaylizer we can set multiple clock frequencies if you have a switch outside the FPGA. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf page 7.

However, since yours is related to dynamic reconfig of an PLL, What you can do is look into the example design https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf download the pll_reconfig_mnc.qar see how they constrain the sdc. If there are nothing inside, means they expect customer to test it on their hardware to make sure it works.

[Kenny_Tan]

Since this thread had been mark as accepted solution, we shall close this thread. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.