SDRAM in SOPC system

[Altera_Forum]

Hi, 

I need to use SDRAM as main memory with CycloneIII device. My whole code will be executed on SDR SDRAM (8 Mbytes). so need some guidance on how to integrate SDR SDRAM in niosii based system.   In SOPC component integration, I have added SDRAM controller. Now don't know how to define vector address and exception address for NIOS II cpu configuration.  Kindly help me to clear this issue.

[Altera_Forum]

--- Quote Start ---   In SOPC component integration, I have added SDRAM controller. Now don't know how to define vector address and exception address for NIOS II cpu configuration.   --- Quote End ---   Opening properties window for Nios II component in SOPC builder, you can simply select where you want to place them. Read the SOPC tutorial  http://www.altera.com/literature/tt/tt_nios2_system_architect.pdf

[Altera_Forum]

You will want your exception address to be located in the SDRAM (assuming that is where you'll be running your code). Your reset vector relies entirely how you plan on booting your system. So as you know SDRAM can't be powered up with initialized contents. You need a bootloader that will copy your application from a non-volatile location (usually flash memory) to your main memory (SDRAM). 

 Using the Nios II tools you can use any memory you like to download your code, but when you go to deploy your product you won't have the luxury to just simply download to whatever memory you want. So what is your bootup scheme in your final project? Whatever will be your final implementation I recommend prototyping as early as possible.

[Altera_Forum]

Yes, this is for prototype development board, not any product. 

And I am learning all the aspects with FPGA development. My development board has EPCS memory, Micron's SDR SDRAM, Cycloneiii FPGA on board. Right now, I am experimenting with SDR SDRAM, EPCS will come into picture at later stage. Currently, i just want to run all my SOPC code and NIOS application code on SDRAM instead of on-chip memory.  Upto now, I have checked all my SOPC code and NIOS application code running with On-Chip RAM without SDRAM or EPCS memory configuration in the system.  Is it not possible to execute the software on SDRAM(as main RAM of the system) without configuring EPCS non-volatile memory?  Regards.

[Altera_Forum]

Since your project is not going into a production system you can run your code out of SDRAM without using flash by downloading your code using the Eclipse tools or command line tools. You can follow the documentation to find out how to download through the GUI but from the command line you run this: 

 nios2-download -g -r <your software .elf file>  (if you do this from the command line and want to open a terminal run this 'nios2-terminal')