SOPC Builder SPI Core

[Altera_Forum]

I want to use the SPOC SPI core to interface to an ADC requiring 24 bit transfers. However, the SPI core only supports transfers upto 16 bit.  

   Is it possible to do two transfers in order to get the full 24 bits without de-asserting the the slave select line (some devices don't like it if you do)? Update.......... Just read in the manual that you can prevent the slave select line from de-asserting between transfers by setting bit 10 in the control register.   Also, how easy is it to do the software programming as Altera state in Ver 8.0 handbook, Volume 5, Section I, & SPI Core:   "The SPI core does not match the generic device model categories supported by the HAL, so it cannot be accessed via the HAL API or the ANSI C standard library. Altera provides a routine to access the SPI hardware that is specific to the SPI core."   The handbook also states:   "This routine is designed for SPI masters of 8-bit data width or less. Currently, it does not support SPI hardware with data-width greater than 8 bits."     Has anyone actually used the core successfully for > 16 bit transfers?   

[Altera_Forum]

So many IC vendors create parts with SPI-like interfaces that deviate slightly from the norm. Just write your own core. SPI is extremely easy to code. 

 Jake

[Altera_Forum]

I don't realy want to write a new SPI core from stratch - I'm relatively new to this. Is it possible to get at the code for the Altera SPI core and modify it? 

 Alternatively, could I just do three 8 bit transfers to obtain the full 24 bits?   Tim

[Altera_Forum]

Chipselect will not be maintained between transfers if you do three 8-bit transfers. If this works with your ADC then you might be able to get away with it. 

 As far as modifying the code. You can try generating the SOPC system then looking at the generated SPI module to see if you can make use of it. I've never done it as it's always been just easier to write my own.  Jake

[Altera_Forum]

I'm sure you can use Control Register bit 10 (SSO) to keep ss_n active for multiple frames, and use 3 x 8 bit transfers. For the software part I'd start off with some simple IORD/IOWR commands to get it working. Once you're happy with that you might want to do it all in interrupts. There have been discussions of using SPI on the Nios forum which may be helpful (try the link below) 

http://forum.niosforum.com/forum/index.php?showtopic=9321&hl=spi

[Altera_Forum]

Thanks for all your help and suggestions. I appreciate it.:)  

 Tim

[Altera_Forum]

Hi tery54  

i want to use the spoc spi core to interface to an adc requiring 24 bit transfers. however, the spi core only supports transfers upto 16 bit. is it possible to do two transfers in order to get the full 24 bits without de-asserting the the slave select line (some devices don't like it if you do)?  I'm using an ADC which outputs 64 bits per sample (4channels á 16bit) via SPI. Therefore I use the Altera SPI core. Configure the core to have 16 bit register and then use the alt_avalon_spi_command() function in your application. BUT before you use it, copy it to your project folder rewrite it to use read and write data width of 16 bit.  orginal: int alt_avalon_spi_command(alt_u32 base, alt_u32 slave, alt_u32 write_length, const alt_u8* wdata, alt_u32 read_length, alt_u8* read_data, alt_u32 flags)  rewritten: int alt_avalon_spi_command(alt_u32 base, alt_u32 slave, alt_u32 write_length, const alt_u16* wdata, alt_u32 read_length, alt_u16* read_data, alt_u32 flags)  Don't forget the adopt the variables in the function to be 16 bit width.  Then call function with: write_length = 0 wdata = dummy pointer (if you only want to read from adc) read_length = 2 (2 times 16 bit) read_data = address of an array with 2 x 16 bit dimension flags = 0 (1 would be merge bit, but this is not necessary here)  Be aware if you want to rewrite the function to read only, by deleting everthing that deals with writing. This won't work. Because the SPI is full duplex and only applies SCLK when it writes to MOSI (you can leave MOSI unconnected in the block diagram in Quartus II). The core reads and write data parallel, but since C is executed step by step, the spi command writes, reads, writes, reads etc. So write zero bytes and leave all code concerning write access, as it is, expect the data width.Depending on the output of the ADC and the configuration of the SPI core regarding transmission of MSB or LSB first, you have to manipulate the two array values to create one 24 bit value out of the two 16 bit values.  kloocki