SOPC Builder generates Verilog but Quartus is set to VHDL

[Altera_Forum]

I had Quartus II 10.1fb installed and everything worked fine. I installed 10.1 and opened an existing project and now it's generating Verilog files instead of VHDL. 

 Quartus II -> Tools -> Options: HDL preference is set to VHDL  SOPC Builder System Generation tab says the following above the "Simulation. Create project simulator files." check box:  "System module logic will be created in Verilog."  What gives? I can't find any way to specify the preferred language in SOPC Builder.

[Altera_Forum]

you select an HDL when you initially create the SOPC Builder system. you can still change it by editing the .sopc file in a text editor. change the line(s) that say Verilog to VHDL

[Altera_Forum]

you select an HDL when you initially create the SOPC Builder system. 

 Right and I'm sure I did that. Somehow when I installed the newer version of the tools and opened the existing project in the new tools, it switched it on me.  you can still change it by editing the .sopc file in a text editor. change the line(s) that say Verilog to VHDL   Perfect! That did the trick! Thanks!