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SOPC Builder hangs on Linux when generating UP IP

Altera_Forum
Honored Contributor II
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I have installed Quartus 8.1 with NIOS and SOPC in Ubuntu 9.04. I can compile, program the DE2 board, an so on (thanks to many mesages from this forum). I have run also the SOPC demo without problems. 

 

I would like to use University Program IPs for DE2 board. I have download zip versions from Altera, installed the components, and set the path to include them in SOPC (I only found a windows installer). They are recognized, and I can include and configure them from the SOPC GUI. 

 

The problem is that SOPC Builder "hangs" when trying to generate any UP component (I have to manually kill the process). 

 

I have already tried: 

- Refresh components and system from SOPC. 

- Generate *.ipx (even moving the UP components to where the main sopc_builder components are, that is /opt/altera8.1/ip/altera/sopc_builder_ip). 

 

If someone can give me a clue about why I'm missing...
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Altera_Forum
Honored Contributor II
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More info on topic. After contacting Altera, they say that Ubuntu is not supported. However, error does not seem related to Ubuntu, because if I run SOPC for non University Pogram components it works perfectly. 

 

Anyway, If I run: > sopc_builder --generate nios_system --debug 

 

then a warning is output before SOPC hangs. 

 

(snip) 

Progress: (validating nios_system) 

Progress: current 955:  

Progress: current 954:  

Progress: (done reading nios_system) 

Progress: Validating... 

Progress: Generating /home/jordi/vhdl/DE2_exemples/DE2_JRB_Demo/nios_system.sopc 

Warning: Switches: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 

Debug: sram: Quartus_map: 0 

Debug: keys: Quartus_map: 0 

Info: vga: Video Output Stream: Format: 640 x 480 with Colour: 10 (bits) x 3 (planes) 

Debug: vga: Quartus_map: 0 

Debug: vga_char: Quartus_map: 0 

Debug: vga_pixel: Quartus_map: 0 

Warning: cpu.data_master/vga_char.avalon_char_buffer_slave: vga_char.avalon_char_buffer_slave does not have byteenables. Narrow (less than 32-bit) writes from cpu.data_master will result in spurious writes to vga_char.avalon_char_buffer_slave 

Info: Wrote /home/jordi/vhdl/DE2_exemples/DE2_JRB_Demo/nios_system.sopcinfo 

Info: sram: Starting Generation of SRAM or SSRAM Controller 

Debug: get_generation_setting: Deprecated command 

Debug: get_generation_setting: Deprecated command 

Debug: get_generation_setting: Deprecated command 

 

Could this be related?
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Altera_Forum
Honored Contributor II
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More on this topic. 

 

After debugging the *_hw.tcl files for UP components, I found that their are prepared for windows only. So, the basic problem consists on files or paths which are not found.  

 

I could avoid the complete hang of SOPC builder by issuing these commands: 

 

sudo ln -s $QUARTUS_ROOTDIR/linux/perl $QUARTUS_ROOTDIR/bin/perl 

sudo ln -s $QUARTUS_ROOTDIR/linux/perl/bin/perl $QUARTUS_ROOTDIR/linux/perl/bin/perl.exe 

 

which create symbolic links for the expected executables in *_hw.tcl. 

 

 

However, there are still more problems to solve. Now I've got errors like: 

 

Info: Wrote /home/jordi/vhdl/DE2_exemples/DE2_JRB_Demo/nios_system.sopcinfo 

Info: nios_system: Wrote /home/jordi/vhdl/DE2_exemples/DE2_JRB_Demo/nios_system.html 

Info: sram: Starting Generation of SRAM or SSRAM Controller 

Error: sram: Generation callback did not provide a top level file (expected `add_file sram.v/vhd/sv {SIMULATION SYNTHESIS}`) 

Info: keys: Starting Generation of Parallel Port 

Error: keys: Generation callback did not provide a top level file (expected `add_file keys.v/vhd/sv {SIMULATION SYNTHESIS}`) 

Info: vga: Starting Generation of VGA 

Error: vga: Generation callback did not provide a top level file (expected `add_file vga.v/vhd/sv {SIMULATION SYNTHESIS}`) 

Info: vga_char: Starting Generation of Character Buffer 

Info: vga_char: /opt/altera9.0/quartus/bin/perl/bin/perl.exe -I/opt/altera9.0/quartus/sopc_builder/bin/perl_lib/ UP_IP_Core_Generator.pl lang=vhdl outdir=/home/jordi/vhdl/DE2_exemples/DE2_JRB_Demo/ name=vga_char files=Altera_UP_Avalon_Character_Buffer.v;Altera_UP_128_Character_Rom.v;Altera_UP_FB_Color_Rom.v;Char_Mode_Rom_128.mif;FB_Color_Rom.mif params=AW:13;DW:8;BUFFER_SIZE:8192;ENLARGE_CHAR:0 sections=USING_DE1:0;USING_FOREGROUND_COLOUR:0;USING_BACKGROUND_COLOUR:0;USING_1BIT_COLOUR:1;USING_4BIT_COLOUR:0;USING_8BIT_COLOUR:0;USING_9BIT_COLOUR:0 

Error: vga_char: Generation callback did not provide a top level file (expected `add_file vga_char.v/vhd/sv {SIMULATION SYNTHESIS}`) 

Info: vga_pixel: Starting Generation of VGA Pixel Buffer 

Error: vga_pixel: Generation callback did not provide a top level file (expected `add_file vga_pixel.v/vhd/sv {SIMULATION SYNTHESIS}`) 

 

I suppose it is related, so there should be an executable/path missing somewhere. If anyone has experience with callback functions, he/she may be of great help. 

 

UPDATE: I've got an answer from Altera regarding the last errors. It seems that they are aware of the errors (so, I suppose it is also the same with windows Quartus 9.0 and UP cores) and they promise to release an updated version of the cores this week. :)
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Altera_Forum
Honored Contributor II
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The new UP cores for 9.0 are available for download on the Altera ftp site at: 

ftp://ftp.altera.com/up/pub/university_program_ip_cores/90/ 

 

I've done a basic test and they build nicely on my Ubuntu system. 

 

So, it seems that this problem is finally solved.
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Altera_Forum
Honored Contributor II
1,086 Views

thankx i was also stucked in same

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