STAP steering vector generation

[Altera_Forum]

hello everyone 

I have run one of DSP builder's reference designs named STAP steering vector generation, the dsp builder made a vhdl code. I changed the inputs to constant signals. and just a clock ,areset and a start signal named go_s are the inputs. the code will work exactly true, as I checked it in Qsim software. but whenever I program it on the stratix EP4sgx device, the outputs which are 32 bit floating point will have zero value has anyone run this refernce design or can you help me checking the vhdl code whhich is attached? thank you so much

[Altera_Forum]

if you connected all the inputs to constants, have you checked that Quartus hasnt removed all the logic?

[Altera_Forum]

thank you for your quick answer 

but what do you mean by removing all the logic? I defined that input signals whith the same name they had before this .

[Altera_Forum]

You mention that all inputs have been connected to constants. Often, if you leave the inputs constant, unless there is complicated logic in between then the output is constant, so no logic will be created or can be removed. Have you checked this.