How to setup clock source constrain

[Altera_Forum]

Hi, 

I am working on a design where I'll have a recovered clock coming in at 2.048MHz. Also, an external PLL is multiplying this clock by a factor of 8 at 16.384MHz and provided to the FPGA. I am using the PLL inside the FPGA (Altera Cyclone III) to divide this down by a factor of 4 to 4.096MHz with a 90degree phase shift. How should I constrain these clock in the .sdc file?  I have the following, but not sure if it's correct or not: create_clock -name ClientRxRClk -period 488.28125 [get_ports {ClientRxRClk}] create_clock -name 8XClientRxRClk -period 61.03515625 [get_ports {8XClientRxRClk}]  create_generated_clock -name 2XClientRxRClk -source [get_ports {8XClientRxRClk}] -divide_by 4 -phase 90 [get_pins {inst1|altpll_component|auto_generated|pll1|clk[0]}]   but I don't see how to specify the relationship between my ClientRxRClk and 8XClientRxRClk (generated by external PLL)  From the compiler, I have the following critical warnings: Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning (332169): From ClientRxRClk (Rise) to 2XClientRxRClk (Rise) (setup and hold)  Critical Warning (332169): From ClientRxRClk (Fall) to 2XClientRxRClk (Rise) (setup and hold)  Critical Warning (332169): From 2XClientRxRClk (Rise) to 2XClientRxRClk (Rise) (setup and hold)    ...any suggestions are welcomed..   Thanks  Yi