Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

[Altera_Forum]

Over the past 30 years I've seen languages come and go. I started programming in assembler, and have since graduated to many 2nd and 3rd generation languages. I tend to shy away from 4th generation tools because I dislike graphical interfaces during programming. Meanwhile the world is going wild using ever more graphical tools to describe processes to make it easier to model/manipulate/program. 

 Enter the electronic design world. I've designed (mostly digital) circuits in the eighties, using schematic entry. Then I return to digital design these days and find that schematic entry is frowned upon, and using VHDL/Verilog is deemed "more professional".  Can someone explain to me why schematic entry (which, from a pure programming standpoint could be considered a 4th generation entry-tool) is considered inferior to VHDL/Verilog (which, from a pure programming standpoint, could be considered 3rd generation entry-tools)?  I've looked at VHDL/Verilog, and even though they work for me, I find that they make it more difficult for me to envision (gate)delay characteristics and clock domains than when I'd use schematic entry/building blocks. Schematic entry supports a fairly straightforward left-to-right/top-to-bottom processing workflow; VHDL/Verilog however tend to result in spaghetti-like codeflows (because of the parallel nature of the hardware description), which makes design errors more likely... Unless, someone is able to envision the schematic equivalent in his head while kranking out VHDL, but then using VHDL is more of a nuisance than an advantage.  VHDL has its place for complicated table driven logic which isn't easily described in functional blocks, but other than that, it makes it more difficult to envision the hardware equivalent than using schematic entry and thus hinders productivity.  Could anyone more proficient than I am in VHDL/Verilog, comment on my assertions above?

[Altera_Forum]

--- Quote Start ---  I think thats rather unfair. Technology today is much different. People have to deal with generating large multi-dimensional filters with complex memory controllers and other complex interfaces (as an example). Id hate to see anyone try to create large FPGA designs using 74 series chips. The best engineers I know still understand all the old school stuff, but are much happier today in the HDL world. They all know what kind of resource usage they will be looking at without even writing a word of HDL code.  --- Quote End ---    There is no fair/unfair about it--it's a worldview transition. To those of us who have run the evolution spanning TTL-PAL-GAL-PLD-CPLD-FPGA, we see the advantages of staying close to the hardware, whether the ultimate design connectivity be with discrete wires, fuses, or LUT patterns and routing channels.  I'm not going to fall for the "let's all return to the 7400 logic era" straw man. I was there, and, barring a few clever things done very efficiently with a few gates & FFs, those were not the good old days.  But, abandoning a fundamental understanding and feel for hardware, moving incrementally away from a GUI-based design (schemata) into reams of code, leaving everything to be sorted by some magic compiler, seems imprudent and risky. Funny how GUI is all the rage in so many technical arenas, yet engineers are being squeezed ever more into command-line, lines-of-code abstractions.  Hardware engineers generally favor assembler programming because it's closer to the hardware. Software wonks don't care as long as they get to play with highly-abstracted structures: just throw more memory and peripherals at them to keep 'em happy--let the compiler do the dirty work. Same with the FPGA specialist nowadays: just another wonk cranking out code.  And I'll contradict you on being "much happier" in HDL land--if I were so delirious with joy I wouldn't be writing this. Sure, HDLs solve problems in parameterization and state machine design that would be intractable and unmaintainable with primitives. But like so much software, I've seen HDL code that's poorly structured, uncommented, and with hidden complexities and interlocking states that cannot be easily understood at a glance.  Not everybody is doing million-gate, high-volume designs, yet for FPGA companies like Altera that's where the money is. They want to kick small operators into the gutter to save a few bucks, fine. But just because some pointy-haired VP thinks it's okay while cashing in his bonus does not IMO compensate for the loss of goodwill toward what is becoming just another FPGA vendor, rapidly losing its edge.  //atemp99

[Altera_Forum]

I still stand by my point of the source control being a major advantage to using a text based language. Until you can find me a diff program that will work with a schematic entry, and tell me the actual connection changed rather than just when i move a block one pixel to the left, i might start to be influenced. 

 kevin

[Altera_Forum]

--- Quote Start ---  But like so much software, I've seen HDL code that's poorly structured, uncommented, and with hidden complexities and interlocking states that cannot be easily understood at a glance.  --- Quote End ---   I have some example of old schematics based FPGA designs that are uncommented, unmaintainable and extremely difficult to understand when you aren't the person who wrote them. What's your point? You can write bad code in any language, and have schematics that look more like a spaghetti plate than hardware. Similarly you can have very clean schematics or very elegant HDL code.

[Altera_Forum]

--- Quote Start ---  I have some example of old schematics based FPGA designs that are uncommented, unmaintainable and extremely difficult to understand when you aren't the person who wrote them. What's your point? You can write bad code in any language, and have schematics that look more like a spaghetti plate than hardware. Similarly you can have very clean schematics or very elegant HDL code.  --- Quote End ---    As have I - and the people that produced them had 20-30 years experience in hardware/FPGA design and understood very well how basic elements worked. When it came to trying to modify their designs, I wished a well organised code monkey had done it instead.

[Altera_Forum]

Hi BuGless. This is mainly about your comment about old timers thinking parallel(overlapped) design. The attached .qar is for what I dubbed CEngine which is a cpu that does if/else, for, do/while, function/subroutine call, and expression assignment. Also there is a .txt which is a cycle log showing some code and the cycle by cycle execution. (I hope both are attached). 

One other significant point is that DCT and Xilinx just made news in EE Times with a Java cpu.A while ago I posted CEngine in this forum and got 1 response but maybe this time. The design is not completely connected on the bdf, but there is a running "simulator". Variables are in a 3 port ram so the first two operands are immediately available when the statement and operator appear. In parallel if there is a conditional jump that address is available at the end of the first execution cycle. If the jump is not taken the next statement i available so branch or not, it takes one cycle.

[Altera_Forum]

hi  

I need a simple calculator with -,+,/,* operation & logic operation & shift right & shift left that I enter digits from keyboard and show them on lcd.So I must have keyboard component and lcd component for digits (VHDL). can u help me? I've found calculator codes from this site but that doesnt have logic and shift operations. please help me. I cant find component lcd and keyboard from internet. Can you give me codes of this calculator that I want? please help me. thanks a lot

[Altera_Forum]

I won't be able to help much. Here are a couple of ideas, since you have found calculator code why not edit the code to add the functions that you need? There is a shiftregister megafunction that you could instantiate and would need one for right and one for left. Then the kind of shift you would have to add the gating and controls for signed/unsigned, arithmatic/logical etc.  

As far as the keyboard and display maybe you could use something like the B-Micro that has a USB interface to your PC so there may be a way to use the PC keyboard and display. Even if you had a full description of what you are building, I would be of little help because I am not skilled in VHDL. Wishing I could be of more help, Good Luck.