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Valued Contributor III
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Schematic highs and lows

Are there any simple ways to force a schematic signal to logic HIGH other than tying it to VCC symbol? How about forcing a logic LOW other than tying to a GND symbol?

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Valued Contributor III
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Re: Schematic highs and lows

 

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Are there any simple ways to force a schematic signal to logic HIGH other than tying it to VCC symbol? How about forcing a logic LOW other than tying to a GND symbol? 

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The you mentioned above is the simplest way. Also, you can define a middle signal which is connected to VCC or GND, then you can use this middle signal as the high or low.
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Valued Contributor III
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Re: Schematic highs and lows

I think what Jerry meant was that you could connect a net to VCC or GND and call it something like LOGIC_HIGH. Then label any net you want connected to it also LOGIC_HIGH. 

 

As a quick reference, if you were using HDL, connecting to high or low is as simple as: 

 

some_sig <= '1';
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Valued Contributor III
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Re: Schematic highs and lows

 

--- Quote Start ---  

I think what Jerry meant was that you could connect a net to VCC or GND and call it something like LOGIC_HIGH. Then label any net you want connected to it also LOGIC_HIGH. 

 

As a quick reference, if you were using HDL, connecting to high or low is as simple as: 

 

some_sig <= '1'; 

--- Quote End ---  

 

Yes, as attached image shows!
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Valued Contributor III
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Re: Schematic highs and lows

hmmm... not sure the thumbnail is technically legal since the VCC and GND are single signals (although it may still work). It would be OK for that purpose, but for a bus I would use the primitive lpm_constant.

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Valued Contributor III
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Re: Schematic highs and lows

You can connect a bus to GND/VCC without a problem. 

Any reason you're using schematics and not HDL?
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Valued Contributor III
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Re: Schematic highs and lows

Just an old-timer doing some relatively frequency and pulse generation - 24 programmable counters and one-shots. Easier for me to do in schematics (the ldm_xxx Megafunctions work great) then trying to control synchronized counters in HDL.

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