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15478 Discussions

Serial flash Loader IP core

QWE
Beginner
259 Views

Move the code of my project from Cyclone V to Cyclone 10 GX and got warnings (16479 & 13228):

Warning(16749): Verilog HDL warning at alt_sfl_enhanced.v(161): identifier dclkin_without_sdr is used before its declaration

...

Warning(13228): Verilog HDL or VHDL warning at alt_sfl_enhanced.v(93): formal port 'jtag_state_sdrs' has no actual or default value

This warnings are just few of the received(36 in all).

I dont care about 16479, but what's problem with 13228?

*Declaration of module (altera megafunction)*

module alt_sfl_enhanced
(
// Hub IOs
ir_in,
ir_out,
tdi,
raw_tck,
usr1,
jtag_state_sdrs,
jtag_state_sdr,
jtag_state_udr,
jtag_state_rti,
tdo,

// ASMI IOs
dclkin,
scein,
sdoin,
data1in,
data2in,
data3in,
data0oe,
data1oe,
data2oe,
data3oe,
asmi_access_request,
data0out,
data1out,
data2out,
data3out,
asmi_access_granted

i am using Quartus Prime pro 19.4. How to desable messages or solve problem?

 

0 Kudos
3 Replies
YuanLi_S_Intel
Employee
243 Views

Hi Sir,


During device migration, have you performed IP upgrading? Also, have you tried on the actual design? Does it has any impact on the functionality.


Thank You


QWE
Beginner
236 Views

I can't answer about functionality, have latest version of the program (Quartus Prime Pro 20.2).

YuanLi_S_Intel
Employee
210 Views

Probably you will need to reinitiate the IP as some of the pin is not the same between cyclone v and cyclone 10


Reply