On-chip memory on Stratix 10

[LucaGiambastiani]

Hello,

We are porting a project from Arria V (Quartus 16.1) to Stratix 10. The original one used the on-chip RAM memory IP with dual clock and Avalon-MM interfaces. It appears that this type of IP is present with single clock only, in the IP catalog for the Stratix 10 on Quartus Pro 20.1.

Is there available this kind of components for the above version of Quartus Pro? Or there is a way of emulating this component?

Thanks,

Luca

[SyafieqS]

Hi Luca,

Yes, there is a feature in S10 so called True Dual Port Dual Clock Emulator (TDP) to emulate TDP dual clock mode. You must turn on this feature in parameter editor of dual-port RAM IP core. May refer to link below for details

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf (pg-20)

Thanks,

Regards

[LucaGiambastiani]

Hello Syafieq,

Thanks for the reply.

We think that there are two problems with the TDP emulator. First, we need a memory with Avalon-MM interfaces, while the dual port RAM seems to have only conduit interfaces. Second, the page you linked says that the latencies are not guaranteed with a clock ratio less than 7. In our case the frequencies are 220 MHz and 250 MHz, so a ratio way below 7.

Is it possible to configure this IP component in a way that is compatible with an Avalon-MM interface?

Thanks,

Luca