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BIdro
New Contributor I
179 Views

Driver Dedicated Transceiver Pin

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Hi,

I'm using Quartus Prime Software to program a Cyclone V GT FPGA.

I want to drive a differential pair of dedicated transceiver pins ( for example transmit a signal clock or packets without any IP). How can I do that?

Thanks for the help.

Bryan

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1 Solution
Deshi_Intel
Moderator
158 Views

HI Bryan,


Your questions is too high level but let me try my best to answer.


In general, I advise you to checkout the IP in user guide doc first as different IP solution may have its own design requirement.


Now to your questions

  1. In the Cyclone V family, is the IP compatible with GT/GX only? 
  • The IP can be used for both GT/GX channel.
    • Main difference is the supported data rate
  1. When I use the IP, do I also have to define time constrains?
  • The IP already has its own timing constraint but you still need to constraint your FPGA core own design logic path that interact/connect with the IP block.


Thanks.


Regards,

dlim


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3 Replies
Deshi_Intel
Moderator
169 Views

Hi Bryan,


Unfortunately you can't.


The only way to access and interact with Transceiver channel is via Altera transceiver IP solution (popular transceiver PHY IP is like customer PHY IP or NativePHY IP)


You can check out the detail of transceiver IP in below user guide doc link.


Thanks.


Regards,

dlim


BIdro
New Contributor I
164 Views

Hi Dlim,

thank you for the response.

Ok, I will use the IP but I have 2 questions:

1) In the Cyclone V family, is the IP compatible with GT/GX only? 

2) When I use the IP, do I also have to define time constrains?

Thanks.

Bryan

Deshi_Intel
Moderator
159 Views

HI Bryan,


Your questions is too high level but let me try my best to answer.


In general, I advise you to checkout the IP in user guide doc first as different IP solution may have its own design requirement.


Now to your questions

  1. In the Cyclone V family, is the IP compatible with GT/GX only? 
  • The IP can be used for both GT/GX channel.
    • Main difference is the supported data rate
  1. When I use the IP, do I also have to define time constrains?
  • The IP already has its own timing constraint but you still need to constraint your FPGA core own design logic path that interact/connect with the IP block.


Thanks.


Regards,

dlim


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