Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Готово! Подписка добавлена.
Готово! Подписка удалена.
Извините, вы должны пройти верификацию для завершения этого действия. Нажмите ссылку верификации в своем электронном сообщении. Вы можете повторить отправку через свой
профиль.
Your questions is too high level but let me try my best to answer.
In general, I advise you to checkout the IP in user guide doc first as different IP solution may have its own design requirement.
Now to your questions
In the Cyclone V family, is the IP compatible with GT/GX only?
The IP can be used for both GT/GX channel.
Main difference is the supported data rate
When I use the IP, do I also have to define time constrains?
The IP already has its own timing constraint but you still need to constraint your FPGA core own design logic path that interact/connect with the IP block.
The only way to access and interact with Transceiver channel is via Altera transceiver IP solution (popular transceiver PHY IP is like customer PHY IP or NativePHY IP)
You can check out the detail of transceiver IP in below user guide doc link.
Your questions is too high level but let me try my best to answer.
In general, I advise you to checkout the IP in user guide doc first as different IP solution may have its own design requirement.
Now to your questions
In the Cyclone V family, is the IP compatible with GT/GX only?
The IP can be used for both GT/GX channel.
Main difference is the supported data rate
When I use the IP, do I also have to define time constrains?
The IP already has its own timing constraint but you still need to constraint your FPGA core own design logic path that interact/connect with the IP block.
