Set GPIO pins with multiple voltage levels

[Altera_Forum]

Hello, 

 I am using a DE0-Nano FPGA and Quartus II 14.0.   I am able to set the voltage of GPIO pins to either a high or low value based on a binary string of 0s and 1s.  However, I would like to set 3 different voltage levels. How do I go about doing this?  And since I can't use a binary string for 3 different values, how do I store the voltage sequence I wish to transmit?  I was considering using a mixer to mix 2 different signals and output 3 different voltage values: e.g.  0,0 -> 0 1,0 and 0,1 -> 1 1,1 -> 2  However the web version of Quartus I have does not have such a mixer function. If this is a good way of approaching the problem where can I get a mixer module?

[Altera_Forum]

As far as I know, this is not possible. FPGAs are binary devices. They output a voltage level or ground (or floating, of course). That's it. 

 You could just encode the two bits to the three values, like you've specified. Why do you need an extra voltage level?

[Altera_Forum]

I am experimenting with different ways of sending data as part of a research project. If an FPGA is not the right device for sending multiple voltage levels what would be a good device that I could use for this? 

 Also as mentioned in my previous post is there is a signal mixer block in Quartus that I could use to mix 2 voltage values and output 3 voltage values? If so where can I find this.

[Altera_Forum]

No such IP exists because FPGAs can't output 3 levels.

[Altera_Forum]

Not strictly true. Using the tri-state output capability, one could transmit a HIGH level (ie, ~3.3V), a LOW level (~0.0V), and a MID level (~1.65V) by having equal value resistive pullup/pulldowns attached to the signal net to set the mid level (ie, having a 3.3K pullup and 3.3K pulldown on the signal line). So one could theoretically have tri-level signaling with a standard FPGA output, at close to the maximum data rate (subject to the RC time constant of the net). 

 Detecting the tri-levels at an FPGA input however is another matter. No FPGA inputs are setup for other than bi-level signal detection.  If your data rate is very slow, you could use PWM encoding on a signal net, and RC filter it to approach what an digital to analog converter would produce. Generating 16 to up to 256 levels should be possible, but the data rate would necessarily have to be very low (1KHz or less). Noise budget would need to be carefully considered, as 256 levels at 3.3V is about 12mV per level. Detection would again be an issue, and would require an A/D and careful circuit design.  So it can be done if you can live with the significant limitations.

[Altera_Forum]

sstrell correctly emphasized that the FPGA pins are purely digital. To generate other voltage levels than "0" (GND) and "1" (VCCIO, you need external analog circuitry, e.g. resistor networks or filters when utilizing modulation. Respectively there's no thing like a mixer block.