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Valued Contributor III
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Set undriven outputs to VCC / GND

Hello, 

 

Does exist some option that allows to set all unused outputs to VCC/GND ? 

Thanks.
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Valued Contributor III
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--- Quote Start ---  

 

Does exist some option that allows to set all unused outputs to VCC/GND ? 

 

--- Quote End ---  

 

There used to be, and you should NEVER EVER use this option. 

 

Why? Consider the case where you have a board with lots of I/Os connected to external devices, eg., a processor. Now lets say you create a "blinky LED" design that uses the clock and LEDs, and you set all other I/Os as driven to VCC or GND.  

 

Q: What do you think happens to your board when you configure the FPGA? 

 

A: It powers up ever so briefly before the driver conflicts on the FPGA and the external devices cause the FPGA to get so hot that it is destroyed. 

 

Yep, I learnt this one the hard way. The precursor to Quartus (MAX+Plus II) had the default to drive unused I/Os to ground. 

 

I repeat NEVER EVER define unused I/Os as GND/VCC! 

 

Cheers, 

Dave
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Valued Contributor III
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During configuration most FPGA devices will drive any outputs to the high impedance state, possibly with a very small pullup current source connected (ie, they don't really 'float'). 

 

There are set options to drive unused outputs low but this is not a direct, low impedance connection to GND, but just the output driving a low at a 10-25ma current or so. 

 

I have never seen any device from any vendor that allows a pin to be programmatically connected direct to VCC or GND as if it were a power pin, for the reasons cited by the previous poster.
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Valued Contributor III
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--- Quote Start ---  

There used to be, and you should NEVER EVER use this option. 

 

Why? Consider the case where you have a board with lots of I/Os connected to external devices, eg., a processor. Now lets say you create a "blinky LED" design that uses the clock and LEDs, and you set all other I/Os as driven to VCC or GND.  

 

Q: What do you think happens to your board when you configure the FPGA? 

 

A: It powers up ever so briefly before the driver conflicts on the FPGA and the external devices cause the FPGA to get so hot that it is destroyed. 

 

Yep, I learnt this one the hard way. The precursor to Quartus (MAX+Plus II) had the default to drive unused I/Os to ground. 

 

I repeat NEVER EVER define unused I/Os as GND/VCC! 

 

Cheers, 

Dave 

--- Quote End ---  

 

Ok, thanks Dave. 

So, the only option to avoid a weak glow of LEDs on my DE1 terrasic card is to set to '0' the corresponding ports programmatically (e.g. in "Initial" section or with "assign") ?
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Valued Contributor III
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Setting unused pins as "outputs driving ground" has been the default choice in old Quartus versions. The reasoning in device handbooks was that the pins can act as additional ground connection to reduce ground bounce, which has some relevance for old packages like PQFP but is no longer reasonable for BGA packages with plenty of redundant GND pins. Although the additional ground connection is through output transistors, it surely shares some of the dynamic currents during switching. 

 

But as Dave explained using the option is prone to damage FPGAs and external logic by shorting signals inadvertently. 

 

It's not a big thing to set unused but externally connected pins to a specific level. Tri-state without weak pull-up (regular input) or tri-state with bus hold could be a safe alternative to driving it low. 

 

The weak pull-up feature of unconfigured pins suggests to define all outputs active low rather than active high, by the way. Doing so, an unused but externally connected pin will be inactive without specific measures.
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Valued Contributor III
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Hi Pavel, 

 

--- Quote Start ---  

 

So, the only option to avoid a weak glow of LEDs on my DE1 terrasic card is to set to '0' the corresponding ports programmatically (e.g. in "Initial" section or with "assign") ? 

--- Quote End ---  

 

 

Initial sections are not always synthesizeable. I did some tests with Synopsys, ISE, and Vivado and got different result. The way I recommend for driving a static value of 1 or 0 from an I/O pin would be to use an assign statement. You could also technically use the following SystemVerilog 

logic led_out = 8'h55; assign led = led_out;  

 

but the synthesis tool will likely warn you that it is using the default value. To avoid that, you can just assign the value you want directly. 

 

Depending on the FPGA, there are several options for unused I/O pins, eg., weak pull-up or weak pull-down. Download de1_basic.zip from this thread: 

 

http://www.alteraforum.com/forum/showthread.php?t=35687 

 

Take a look at constraints.tcl, and you'll see these two options ... 

 

# Tri-state unused pins set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED" # set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED WITH WEAK PULL-UP"  

 

Cheers, 

Dave
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