Setting Constraints for rgmii ethernet PHY

[Altera_Forum]

I would like to ask for help on how to set the output_delay for setup and hold constraints (timequest) for triple speed ethernet. 

For now I just want to analyze the tx side.  1)I have a cyclone5GT dev board 2)the board uses ethernet phy Marvell-Alaska-Ultra-88E1111-GbE. 3)the board is configured for RGMII operations.  The TXsignals from FPGA to PHY are tx_rgmii(3 downto 0) and tx_control. These signals come from the IP module triple speed ethernet, and are connected to the FPGA pins. The tx clock is named GTX_clk and come from an output of a pll (125 MHz) through a ALTERA_DDRBUFFER. The pll output clock drives the alt_ddrbuffer and it drives the fpga_pin GTX_clk.  The create_clock is ok. The derive_pll_clocks is ok.  Now i send the sdc commands:  # **************************************************************# Create Generated Clock# **************************************************************  create_generated_clock -name {gtx_clk} -source [get_pins {myddr1|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {mypll1|pll1_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk} [get_ports {gtx_clk[0]}]   Now i must create the delay outputs (i write only the tx_control constraints for clarity) and the delays are DDR, rising clock and falling clock.  set_output_delay -add_delay -max -clock [get_clocks {gtx_clk}] 1.000 [get_ports {tx_control}] set_output_delay -add_delay -min -clock [get_clocks {gtx_clk}] -0.800 [get_ports {tx_control}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {gtx_clk}] 1.000 [get_ports {tx_control}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {gtx_clk}] -0.800 [get_ports {tx_control}]   with these commands, the fitter does not respect the hold time (slack is negative). No problem with setup time (slack positive).    If i add these commands the compilation make timing constraints OK, but i'm not sure if these command are OK:  set_false_path -hold -rise_from [get_clocks {mypll1|pll1_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk}] -rise_to [get_clocks {gtx_clk}] set_false_path -hold -fall_from [get_clocks {mypll1|pll1_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk}] -fall_to [get_clocks {gtx_clk}] set_false_path -setup -rise_from [get_clocks {mypll1|pll1_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk}] -fall_to [get_clocks {gtx_clk}] set_false_path -setup -fall_from [get_clocks {mypll1|pll1_inst|altera_pll_i|general[0].gpll~pll_output_counter|divclk}] -rise_to [get_clocks {gtx_clk}]   In this case the sum of setup slack and hold slack is greater than 8 ns, and I think it is not possible with a ddr 125 mhz.  I hope you can help me, best regards, Luca.