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Altera_Forum
Honored Contributor I
819 Views

Signal Tap II Terasic Blaster Compatibility

System: 

Quartus Prime V16.1 

HW: Cyclone V product board with JTAG header. 

FPGA Design: A Qsys system with JTAG to Avalon Master bridge, OnChip memory, Clock Source, and System ID Peripheral 

 

I can configure the FPGA using the Terasic Blaster. 

 

Problem: 

On Signal Tap, whenever i run an analysis, i get a status of "Invalid JTAG hardware". This is after i setup my System Console and attempt to write to an On-Chip RAM. I execute System Console from Qsys and run the following: 

1. set mm [ lindex [ get_service_paths master ] 0 ] 

2. open_service master $mm 

3. master_write_32 $mm 0x10 0xAB (Signal Tap hangs after System Console attempts to execute transaction for 60 secs.) 

 

Alternative command sequence: 

1. set jd_path [lindex [get_service_paths jtag_debug] 0] 

2. set m_path [lindex [get_service_paths master] 0] 

3. set claim_path [claim_service master $m_path ""] 

4. master_write_32 $claim_path 0x10 {1 2 3 4} (signal tap hangs after this as well...) 

 

 

Google search resulted with issues on Invalid JTAG Configuration, not "hardware". Is using a Terasic USB Blaster the problem? 

 

Thanks!
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3 Replies
Altera_Forum
Honored Contributor I
39 Views

Using both System Console and Signal Tap simultaneously on the same JTAG can be tricky. Have you tried connecting and starting the analysis in Signal Tap first before using System Console?

Altera_Forum
Honored Contributor I
39 Views

Thanks for the quick reply sstrell! I didn't realize that there would be conflict with simultaneous use of Signal Tap and System Console!  

 

Your suggested sequence is what i've been doing. Configure the FPGA through Signal Tap, then start the analysis, then run System Console through Qsys then run the sequence of commands on System Console.  

 

The reason i'm doing this is I'm having issues accessing the registers on my design using System Console, which is why i tried to debug it using Signal Tap. Without signal tap, I'll configure FPGA through Programmer, run System Console through Qsys, then run the same sequence as what's on my first post, then i get this register access error: 

 

SEVERE: master_write_32: This transaction did not complete in 60 seconds. System Console is giving up. 

 

Clock and reset are verified OK. 

 

I've already scaled down my design to just a JTAG to Avalon Master Bridge with On Chip Memory. Might be my TCL command sequence??? 

 

Thanks!
Altera_Forum
Honored Contributor I
39 Views

Issue solved. External reset source is asserted(inverted logic)!

Reply