"j" is not a constant in verilog for loop addition

Altera_Forum · ‎02-15-2018

Hello,

I am trying to make a simple for loop to add up a parameterizable count of numbers, all in the same clock cycle( I am aware that this may not fit in a single cycle, I may split it up later to more cycles if timing issues arise.). What I am trying to do in essence is(for 3 numbers):

always@(posedge clk) out=in+in+in;

I am getting the error: "j is not a constant".

I am sure there is a method to do this, am I trying to do this in a wrong way?

My full code is:

module mymodule# (
    parameter maxIter = 9,
    parameter bitCount = 16
)(
    input wire clk,
    input wire  in,
    output reg  out
);
initial begin
    out=0;
end
integer j;
always@(posedge clk)begin
    for (j=0; j<maxIter; j=j+1) begin
                // I have tried this
                // out= out + in;
                // Then on a forum I found this
        out= out + in;
                // Neither works
        end
end
endmodule

Altera_Forum · ‎02-15-2018

You want

out= out + in[bitCount*j +: 16];

Altera_Forum · ‎02-15-2018

rozatib

Verilog specifies that if you are taking a slice, one of the indices must be a constant.

Altera_Forum · ‎02-16-2018

Thank you very much, problem solved.