Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Signal Tap logic analyser issue

Altera_Forum
Honored Contributor II
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I am using Cyclone IV E (EP4CE6F17C7N) on my custom built board. I programmed the device with a simple .sof file using Quartus II 11.0 Web Edition via USB Blaster using Programmer tool.  

 

my board is working fine, I can see this by looking at the leds flashing on the board.  

 

there are several state machines in my design and I want to have a look at the signals, so I used Signaltap II logic analyser.  

 

I have added the instances and clock, when I try to program it from the analyser, It failed to do so. It is able to download the .sof. 

I tried to Analyse [RunAnalyse/AutoAnalyse], SignalTap says "JTAG Communication Error" and also says "instance not found". 

 

I understand that the FPGA is getting configured but not initialized. 

 

What am I missing here? What should I do to make the FPGA work? 

 

I request you people to help me getting out of this issue. 

 

Please let me know if you need any further details to find out this issue.
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Altera_Forum
Honored Contributor II
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My best suggestion is to make sure that the SignalTap file is associated with the Quartus project. The actual SignalTap file may not be identified in the Assignments --> Settings --> SignalTap File Section. -James

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Altera_Forum
Honored Contributor II
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Thanks for your reply James, I just checked and the file is included. It is not even programing from signaltap II logic analyser, it does work directly through Programmer. 

 

currently 75% of LE`s are utilized by the FPGA, how many resources does Signaltap analyser uses? does any one has an idea over this ? 

 

I think this could be the issue...
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Altera_Forum
Honored Contributor II
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The LE and RAM resources consumed by SignalTap II are precisely listed in the SignalTap window. As long as the design can be succesfully compiled, there should be no problem. Compile times usually increases when resources run short, also timing closure possibly becomes more difficult. 

 

The reported problems are clearly of a different kind. Getting "Instance not found" repeatedly normally means, that the FPGA has been configured with a different design than that containing the SignalTap II instance. 

 

In some cases, JTAG signal integrity issues prevent correct SignalTap operation although the design can be (mostly) configured correctly. Additional interferences emitted by the design in operation are the most popular reason for this behaviour. But SignalTap II error messages are different in this case, if I remember right.
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Altera_Forum
Honored Contributor II
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When you use SignalTap make sure that the correct device is selected in the "Device" box, just above the SOF Manager. 

You may get this message if, for example, you have 2 devices in your JTAG chain (such as a MAX device and a Cyclone IV), and the device selected is MAX, instead of Cyclone IV, which you're trying to debug. 

Make sure the device that is selected is Cyclone IV. 

 

If this doesn't help, you can also click on "Scan Chain" and then select the correct device in the Device box.
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