I am working on a Cyloone IV design which uses the altlvds megafunction.
The output clcok of this megafunction is called rx_outclock.
In my verilog code it is assigned to a signal called lvds_a_clk_rx_par.
Here is the call to the altlvds function:
altlvds_rx_28bits altlvds_rx_28bits_serdes ( // need to check lpm parameters: input data rate, channels 5, etc?
.rx_in ( lvds_a_rx_ser[3:0] ),
.rx_inclock ( lvds_a_clk_rx_ser ),
.rx_out ( { rx_pair3_28bits[6:0], rx_pair2_28bits[6:0], rx_pair1_28bits[6:0], rx_pair0_28bits[6:0] } ),
.rx_outclock ( lvds_a_clk_rx_par )
);
This clock (lvds_a_clk_rx_par) is used later in the verilog code to clock registers.
When I go into Timequest to check timing and set up constraints I cannot find this clock.
The clock that does show up instead is this:
altlvds_rx_28bits_serdes|ALTLVDS_RX_component|auto_generated|lvds_rx_pll|clk[2]
I can set constraints to this clock and it seems to work ok.
I tried to rename this clock to lvds_a_clk_rx_par in the sdc file with the -name option in the create generated clock statement, but that did not work.
Is there a way for Quartus and Timequest to use the signal names in my Verilog design file instead of the altlvds auto generated names?
