Signal probe??

[Altera_Forum]

I am a tyro. When I want to do some simulation to investigate what is happening inside the design, I am frustrated by the warning message "can't find the node XXX". I think the node I am interested in was eliminated in compilation for the purpose of optimization. 

 Then I look to the tool of "Signal Probe", which it's said that can be used for observing internal signals. But it seems only FPGA supports this feature and CPLD such as MAX3000 doesn't? It is surprising! I think there is some technical reason but I really can't figure it out. Can anybody explain it? or provide a good method to observe internal signal of design?

[Altera_Forum]

Hi Steady, 

You say you are doing simulation on the design, from your saying on "can't find the node XXX", I guess you are doing gate/netlist level simulation. I seldom to netlist/gate level simulation, but I have little suggestion for you: 1. probe for node XXX*, normally after synthesis the node name will become xxx~combout or blabla 2. used the following synthesis option to prevent the node to be synthesized away: set_instance_assignment -name implement_as_output_of_logic_cell on -to <node name>  Also, as far as I know "signal probe" should be used for hardware signal probing/debugging.

[Altera_Forum]

Hi Tiande, 

 Thank you for your reply.   I am doing the normal simulation to watch the waveforms. My discription wasn't correct. The messages are like "Warning: Can't find node Puls2Ded_lpm:280|puls2ded_5:$00008|RCON for functional simulation. Ignored vector source file node."  I tried your way by setting the assignment attribute as "Implement as Output of Logic Cell" in Assignment Editor. But the node was still not found by simulator. I think maybe the information of Assignment Editor can explain it: " This option is ignored if it is applied to anything other than a primitive." Because what I want to probe is a node in sub-design, it is very like this option will be ignored.  Yes you are right Signal Probe is for hardware signal. I mixed up them.  Maybe one thread in this forum before have discussed this topic--I just found it. We can use key words such as KEEP, NOPRUNE to set up the synthessis options, if we are using text language to do development. But the project taken over by me was developed with schematics. It seems the only thing I can do is to add pins to the nodes what I want to see.         --- Quote Start ---  Hi Steady, You say you are doing simulation on the design, from your saying on "can't find the node XXX", I guess you are doing gate/netlist level simulation. I seldom to netlist/gate level simulation, but I have little suggestion for you: 1. probe for node XXX*, normally after synthesis the node name will become xxx~combout or blabla 2. used the following synthesis option to prevent the node to be synthesized away: set_instance_assignment -name implement_as_output_of_logic_cell on -to <node name>  Also, as far as I know "signal probe" should be used for hardware signal probing/debugging.  --- Quote End ---  

[Altera_Forum]

This is what the Altera guys say in "QUARTUS ii vERSION 7.2 Handbook Volume 3: Verification", page 1-8 (October 2007).  

 Your node might not appear in the simulation waveform and  might be ignored during simulation. This happens because the  node has been renamed or synthesized away by the Quartus II  software. To prevent this from happening, Altera recommends  using the register and pin nodes to simulate your design  So how are we supposed to simulate conbinational signals?? I think a good solution should exist.

[Altera_Forum]

--- Quote Start ---    ...  Maybe one thread in this forum before have discussed this topic--I just found it. We can use key words such as KEEP, NOPRUNE to set up the synthessis options, if we are using text language to do development. But the project taken over by me was developed with schematics. It seems the only thing I can do is to add pins to the nodes what I want to see.  --- Quote End ---    You don't need to, if KEEP/NOPRUNE is working, in Quartus II you can export you schematics/bdf file as verilog or vhdl under either File>Export or File>Save As Verilog (check to see which one is right, I use it sometime before), and then add the synthesis keyword to the text file. Also can point me to the thread talking on KEEP/NOPRUNE?