Signal tap doesnt recognise most of the entities of my bdf file. Compilation doesn't fit too

[PedroJServian]

Good morning colleagues,

I need your help with a problem I have encountered with Quartus Prime Lite Software while programing my MAX10 FPGA 10M08SCE144I7G. I have made a design in Quartus to manage some semiconductor triggers. I have made designs in vhd that I have converted to blocks and after that, I have put them in bigger blocks. I have been working on this design and when compiling, synthesising, etc... it took about 1 minute and the design occupied 1400 logical units. However, I have made a modification of the design ‘Pulse_Minimum_V4_ind_RESET’ and when I put it in my block diagram and compile I see that it does it successfully but it takes only about 30 seconds and occupies only 500 logical units. When I open signal tap to debug the design, I see that the block ‘BLOQ_MIN_DEAD’ shows me only the instance ‘Generador_Disparos_v1_ind’ inst4 but however the instance of the same block inst5 does not show me and also does not show me the instances of ‘Pulso_Minimo_C4_ind_RESET’ that I have implemented. Honestly, I dont know what is happening because I have never had this kind of problem. I think that it is not only related to signal tap but also with the compilation because now it takes much less logic elements than before. 

I attach you some captures of the design and if you could let me know what could be happening would be a great advance in my development. Thank you in advance

BR, 

Pedro

[sstrell]

Without seeing the design itself, it's hard to figure this out, but most likely, the logic is getting optimized away because it is not connected to anything, like an I/O pin.  If you want to prevent logic from being optimized away, connect its outputs to an actual I/O pin or use virtual pin assignments to create logic "stubs" that will prevent this.

Check the compilation report in more detail.  If logic is optimized away, it's usually mentioned in there somewhere.

[RichardTanSY_Intel]

The likely reason for the reduced resource usage is that some elements were found to contribute nothing to the functionality of the circuit during synthesis and were optimized away.

Check the Compilation Report, Optimization, Nodes Swept Away During Synthesis to ensure there are no major part of your design missing. While it's normal for synthesis to eliminate some registers, a significant reduction in resources usually indicates a design issue.

You mentioned that resource usage dropped after modifying Pulse_Minimum_V4_ind_RESET. I recommend reviewing that modification to check for potential errors.

If you need further debugging assistance, please share your .qar file (Project > Archive Project).

Additionally, I recommend running the design in VHDL instead of BDF, especially as designs become more complex. 

Regards,

Richard Tan

[RichardTanSY_Intel]

Any update on this?

Do you able to resolve the issue?

Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

The community users will be able to help you on your follow-up questions.

Thank you for reaching out to us!

Best Regards,

Richard Tan

[PedroJServian]

Hi Richard,

It should have been something related with what you said but directly I changed the design and it started to work. I honestly don't know what happened in the design.

Thank you for your advice, have a nice day.

BR,

Pedro