Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17249 Discussions

SignalTap II does not capture full sample buffer

Altera_Forum
Honored Contributor II
1,323 Views

Hello, 

 

Whenever I set up SignalTap to have a particular memory buffer (2K, 4K, 8K, or 16K), I am never able to actually capture the entire memory buffer. It seems like I should be able to do this - for instance, Xilinx ChipScope Pro supports this, and the memory is available in the FPGA for a full capture. If I select a 16K memory buffer, I get output sample indices -2 to 14336 rather than 0 to 16384 as I'd expect (or some offset from that due to trigger position). 

 

Is there a way to get the full memory buffer? 

 

Thanks, 

 

Nathan
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
603 Views

The pre-trigger part of the buffer isn't filled, if the trigger occurs before.

0 Kudos
Reply