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SignalTap II problem adding nodes

Altera_Forum
Honored Contributor II
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I've watched the training video, and it looks like the simplest way to tap into a node when using SignalTap is to open the Technology Map Viewer (Post Fitting), find the net, right click it and use the "Add node to signaltap" entry. Unfortunately I don't get an "Add node to signaltap"entry in the context sensitive menu, and I'd like to know why? 

 

I'm using Quartus 10.1 SP1, the design compiles, fits and runs, and SignalTap II works. I'm just really struggling to add nodes.
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Altera_Forum
Honored Contributor II
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Do you have a SignalTap .stp file added to your project? (I'm just taking a guess, but naturally without one, I could see this not showing up). Most people I've seen using SignalTap don't do it this way, since it can be a pain to dive into the Technolofy Map Viewer, sorting through huge lists. I find directly from the .stp file you can add a signal to tap and open the Node Finder, which has a SignalTap (Post Compilation) filter to only look at post-fit nodes. You can wildcard the name you're looking for and hopefully find it much faster.

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Altera_Forum
Honored Contributor II
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Yes, I've got the SignalTap .stp file added to the project. I'm struggling with the node finder in signaltap because I can't figure out the net names. This might be because I have multiple instances of all my design blocks. It doesn't help that the node names end up so long that they barely fit on the screen!

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Altera_Forum
Honored Contributor II
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For post-fit signaltap, you should pretty much only use register names. Combinatorially net names don't make much sense. If doing pre-synthesis, then you can use about anything, as synthesis will make sure the point you've tapped is the output of a cell. (I know I'm not helping with your original question...)

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Altera_Forum
Honored Contributor II
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Thanks, that's still helpful as I'm new to SignalTap. I've certainly got a lot of combinatorial logic!

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Altera_Forum
Honored Contributor II
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Hi Oliver, 

 

if you have written your own code, e.g. in VHDL and you want to "Tap" signals 

which are resolved by the synthesis tool, you can use the attribute keep ! 

 

here is an example:  

 

--------------------------------------------------------- 

-- signal declarations 

--------------------------------------------------------- 

signal cnt : unsigned (3 downto 0); 

 

--------------------------------------------------------- 

-- attribute declarations 

--------------------------------------------------------- 

attribute keep : boolean; 

attribute keep of cnt : signal is true; 

 

 

now, the synthesis tool can't resolve this signal and you will find it in the node list.
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