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Altera_Forum
Honored Contributor I
1,667 Views

SignalTap - II question

problem: Unable to view certain internal registers in SignalTap II 

 

 

i've tried this (added this to my verilog file). i still don't see any of these registers/wire in signaltap. 

 

//one attribute 

//////////////////////////////////////////////////////////////// 

(* keep *) reg [2:0] keep_reg_apple; 

(* preserve *) reg [2:0] preserve_reg_apple; 

(* noprune *) reg [2:0] noprune_reg_apple; 

 

 

(* keep *) wire [2:0] keep_wire_apple; 

(* preserve *) wire [2:0] preserve_wire_apple; 

(* noprune *) wire [2:0] noprune_wire_apple; 

 

 

reg [2:0] reg_apple_keep /* synthesis keep */; 

reg [2:0] reg_apple_preserve /* synthesis preserve */; 

reg [2:0] reg_apple_noprune /* synthesis noprune */; 

 

 

wire [2:0] wire_apple_keep /* synthesis keep */; 

wire [2:0] wire_apple_preserve /* synthesis preserve */; 

wire [2:0] wire_apple_noprune /* synthesis noprune */; 

 

 

//two attribute 

//////////////////////////////////////////////////////////////// 

(* keep *)(* preserve *) reg [2:0] keep_preserve_reg_apple; 

(* preserve *)(* noprune *) reg [2:0] preserve_noprune_reg_apple; 

(* noprune *)(* keep *) reg [2:0] noprune_keep_reg_apple; 

 

 

(* keep *)(* preserve *) wire [2:0] keep_preserve_wire_apple; 

(* preserve *)(* noprune *) wire [2:0] preserve_noprune_wire_apple; 

(* noprune *)(* keep *) wire [2:0] noprune_keep_wire_apple; 

 

 

reg [2:0] reg_apple_keep_preserve /* synthesis keep */ /* synthesis preserve */; 

reg [2:0] reg_apple_preserve_noprune /* synthesis preserve */ /* synthesis noprune */; 

reg [2:0] reg_apple_noprune_keep /* synthesis noprune */ /* synthesis keep */; 

 

 

wire [2:0] wire_apple_keep_preserve /* synthesis keep */ /* synthesis preserve */; 

wire [2:0] wire_apple_preserve_noprune /* synthesis preserve */ /* synthesis noprune */; 

wire [2:0] wire_apple_noprune_keep /* synthesis noprune */ /* synthesis keep */; 

 

 

//all three 

//////////////////////////////////////////////////////////////// 

(* keep *)(* preserve *)(* noprune *) reg [2:0] keep_preserve_noprune_reg_apple; 

(* keep *)(* preserve *)(* noprune *) wire [2:0] keep_preserve_noprune_wire_apple; 

reg [2:0] reg_apple_keep_preserve_noprune /* synthesis keep */ /* synthesis preserve */ /* synthesis noprune */; 

wire [2:0] wire_apple_keep_preserve_noprune /* synthesis keep */ /* synthesis preserve */ /* synthesis noprune */; 

 

 

What is going on? How do I fix this?
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9 Replies
Altera_Forum
Honored Contributor I
102 Views

For a register that doesn't drive anything(so it may be something like a counter I add for debug and just want to SignalTap), I have used stuff like the following without problem. 

(* noprune *) reg [2:0] status_count; 

This just prevents it from being synthesized out, and the register should be available pre-synthesis and post-fit STP. 

 

For a wire, I have used (* keep *). This ensures that it is the output of a LUT and can be tapped post-fit. Wires should not need this if you are doing pre-synthesis tapping. That being said, if a wire would get synthesized out for other reasons, e.g. let's say it doesn't go anywhere, then the keep won't prevent that. You could have it drive a register with the noprune attribute. 

 

That is what has worked for me, but I'm guessing something else is going wrong since your snippets of code seem to try most possibilities.
Altera_Forum
Honored Contributor I
102 Views

What tool version are you using? I'm using 17.0.0

Altera_Forum
Honored Contributor I
102 Views

I've done it in many different versions. I don't think that's the issue.  

What filter are you using to find the nodes, pre-synthesis or post-fit? I'd recommend pre-synthesis at first as it by far is much easier to find stuff, you just have to run a full compile.  

I assume you're able to find many nodes, and it's just a specific one or two that isn't showing up, either because they're synthesized out or because synthesis munges the net name?
Altera_Forum
Honored Contributor I
102 Views

 

--- Quote Start ---  

For a register that doesn't drive anything(so it may be something like a counter I add for debug and just want to SignalTap), 

--- Quote End ---  

 

 

Counter current state (output of flops) is driving counter next state. Technically it is driving something correct? Why is there a need for any of these attributes?
Altera_Forum
Honored Contributor I
102 Views

okay.  

post-fit. 

yes, bunch of them show up, and a bunch of them go away.  

 

I think I don't understand "pre-synthesis". For "pre-synthesis," why do it in signal tap when I can run modelsim simulations?
Altera_Forum
Honored Contributor I
102 Views

If grabbing a register that doesn't get synthesized out, then there should be no need for these attributes. Most SignalTap users never apply these attributes. 

I recommend tapping registers with SignalTap, but if you want to grab a wire and do it post-fit, then the keep is often necessary. 

The only reason to do post-fit is that you don't have to do a full compile again. If you don't mind doing that, then pre-synthesis is much easier. (This is because synthesis can keep any wire you tap or anything like that. Post-fit is the design synthesized down to LUTs and regs, and if a name has been lost there is no way to get it back). 

 

Pre-syntheis and post-fit are separate from modelsim. If you can find the issue in modelsim, that is by far the better way to go. SignalTap is for hunting down bugs that occur in hardware but not in your simulation. That may be because your hardware has cases/complications that are not in your testbench. It may be because you have invalid timing constraints that don't show up in simulation(like a bus passing between two unrelated clock domains). There are all sorts of reasons hardware doesn't work and the user can't find it in their simulations. That is when to use SignalTap. The reason to choose post-fit is that: 

a) You don't have to run a full compile, which can be a pain when it's an 8 hour compile, or: 

b) It's a problem that jumps around, e.g. on one place-and-route you see it, but then you add SignalTap and recompile from scratch(so everything gets a new fit) and the problem goes away. Post-fit allows you to lock down the locations of that previous fit.
Altera_Forum
Honored Contributor I
102 Views

1. I need to understand what these different steps do and how I can use is it to save time (Design to get it working on FPGA). Let me see if I can find info in manual. 

 

2. In the attached image any idea why "state_read" shows up as nice neat 3 width register but "state_write" is just not recognizable. How do I make "state_write" show up as neat 3 bit register?
Altera_Forum
Honored Contributor I
102 Views

For 2., I'm not really sure. I'm guessing some reduction has taken place or something like that(note that only one of them is a register and the other two are combinatorial). Can't really tell from just the screenshot though, sorry.

Altera_Forum
Honored Contributor I
102 Views

I noticed the 1R, and 2C...not sure what to do. Let me turn off optimizations and see what that does....I just want to see a 3 bit register...Really appreciate all the help

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