SignalTap and Cyclone VI

[Altera_Forum]

Hello. I have strange problem with SignalTap and Cyclone IV. There are fault responses. Frequency is low (50 MHz) and I don't know what to do

[Altera_Forum]

Are you sampling on the right clock? Are your observations correct? 

Do you have timing violations(low clock does not mean no timing violations)?

[Altera_Forum]

--- Quote Start ---  There are fault responses.  --- Quote End ---   Try a more meaningful report!

[Altera_Forum]

There is a simple code 

 tp1 <= tp1_as;  process (fpga_reset_h, sys_clk_int) is  begin   if(fpga_reset_h = '1') then  --tp1 <= '0';  tp2 <= '0';  tp3 <= '0';  ser_txd <= '1';  elsif(rising_edge(sys_clk_int)) then  tp2 <= tp2_as;  tp3 <= tp3_as;  ser_txd <= ser_rxd;-- Synchronous Sequential Statement(s)  end if;  end process;    a1 : ENTITY work.spll  PORT MAP  (  areset => fpga_reset_h,  inclk0 => sys_clk,  c0 => sys_clk_int,  c1 => tp1_as,  c2 => tp2_as,  locked => tp3_as  );   There are no timing violations. SCD file contain correct clock constrains.  SignalTap connected to sys_clk_int and tp1, tp2, tp3.  SignalTap start off-loading data at some moment, but I don't see any graphical data. Pressing "Read Data" button gives result that looks like valid data at incorrect trigger condition  Thanks

[Altera_Forum]

I had a similar problem when using a USB blaster that didn't came from Altera and running signaltap on the linux platform. It seemed that some ftdi drivers messed up a bit the data collected from the blaster and it got shifted a bit. I don't know if you are in a similar situation. 

Can you route those signals to an FPGA pin and check them with a scope?

[Altera_Forum]

My USB blaster didn't came from Altera. But I have no any problem with previous design based on Cyclone III family. I use Windows7 

 TP1..3 are testpoints and I checked them with a scope. I didn't see any problems.  Thanks for reply