SignalTapII

[Altera_Forum]

When in the deign process do we use SignalTap? What is its main function? Anything I need to know that I might not find in the manuals that you guys might know from experience?  

 Thanks

[Altera_Forum]

In an ideal scenario, you never use SignalTap. Instead you simulate the design, fix all issues there, and the hardware just does what the sims show. 

I've never seen an ideal scenario though. Something doesn't work, sims don't catch it, and SignalTap is the only way to get in there and figure out what's going on. One thing I like doing is having pre-determined tap points. These are basically locations where the data can be captured and you have a good understanding of what it should look like. You might want to put keep attributes on combinatorial nodes so they can be tapped post-fit. Then, if something goes wrong, you can hook signaltap up to that location, monitor it, and determine if the data is good at that point or not. It's definitely up front work that may not be necessary at the end, so up to you on how much time you want to spend.  Also, don't forget that you can put your top-level partition to Post-Fit, which locks down the whole design, and your SignalTap is a separate partition(by default), so you can tap nodes and monitor them without having to re-place-and-route the whole design. This is useful for quicker SignalTap implementations, and is extremely useful for problems that are build dependent, i.e. where some seeds show the problem and others do not.

[Altera_Forum]

Btw, how to keep combinational nodes available in post-fit? Synthesis attributes?

[Altera_Forum]

Something like: 

(* keep *) wire read_enable; That makes read_enable the output of a combinatorial LUT, so it will affect synthesis a bit(logic can't be moved before/after this point, as it would change the behavior). This wire should now show-up as a post-fit node that can be tapped.

[Altera_Forum]

I usually use virtual pins, but in a big design, with many modules inside it's hard to tap a deep signal...

[Altera_Forum]

Signal Tap is an invaluable tool. In normal algorithm and digital design, each VHDL/Verilog module has a testbench with it. As groups of modules are connected, then the resulting group has a testbench. However, there are times when a small module is added to an overall design and the time and effort of a testbench don't really fit, and Signal Tap can be used to verify the design. In addition, when using A/D converters, Signal Tap is invaluable for verifying the entire analog and digital signal processing chain is working. -James

[Altera_Forum]

You need to view SignalTap as a convenient, build dependent capture system. 

It is has useful trigger system but uses a lot of fpga resource.  With large systems packed into a limited resource, designers tend to have their own capture systems by tapping from various points along processing paths and storing data externally with minimum fpga resource usage.  SignalTap could be big burden on timing/resource critical cases. Its main attraction is either for beginners to see through real time or advanced designers with ample space in their fpga or for an occasional debugging of unexpected issue.