Error(13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/mmdk1_cpu/mmdk1_cpu_nios2_gen2_0/altera_nios2_gen2_unit_191/synth/altera_nios2_gen2_rtl_module.sv'
I'm guessing you've added a Nios to your design. I'd go back to the parameter editor for it and regenerate, then compile again. You can also try deleting the project database folder (db or qdb depending on Standard or Pro edition) and recompiling.
It's hard to suggest anything more than that without knowing more about the design.